51 	struct drm_i915_private *i915;  member
69 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915)  in i915_to_dmc()  argument
71 	return i915->display.dmc.dmc;  in i915_to_dmc()
79 	"i915/" __stringify(platform) "_dmc.bin"
87 	"i915/"					\
296 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id)  in has_dmc_id_fw()  argument
298 	struct intel_dmc *dmc = i915_to_dmc(i915);  in has_dmc_id_fw()
303 bool intel_dmc_has_payload(struct drm_i915_private *i915)  in intel_dmc_has_payload()  argument
305 	return has_dmc_id_fw(i915, DMC_FW_MAIN);  in intel_dmc_has_payload()
309 intel_get_stepping_info(struct drm_i915_private *i915,  in intel_get_stepping_info()  argument
312 	const char *step_name = intel_display_step_name(i915);  in intel_get_stepping_info()
319 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)  in gen9_set_dc_state_debugmask()  argument
322 	intel_de_rmw(i915, DC_STATE_DEBUG, 0,  in gen9_set_dc_state_debugmask()
324 	intel_de_posting_read(i915, DC_STATE_DEBUG);  in gen9_set_dc_state_debugmask()
327 static void disable_event_handler(struct drm_i915_private *i915,  in disable_event_handler()  argument
330 	intel_de_write(i915, ctl_reg,  in disable_event_handler()
335 	intel_de_write(i915, htp_reg, 0);  in disable_event_handler()
338 static void disable_all_event_handlers(struct drm_i915_private *i915)  in disable_all_event_handlers()  argument
343 	if (DISPLAY_VER(i915) < 12)  in disable_all_event_handlers()
349 		if (!has_dmc_id_fw(i915, dmc_id))  in disable_all_event_handlers()
353 			disable_event_handler(i915,  in disable_all_event_handlers()
354 					      DMC_EVT_CTL(i915, dmc_id, handler),  in disable_all_event_handlers()
355 					      DMC_EVT_HTP(i915, dmc_id, handler));  in disable_all_event_handlers()
359 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)  in adlp_pipedmc_clock_gating_wa()  argument
372 			intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),  in adlp_pipedmc_clock_gating_wa()
376 			intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe),  in adlp_pipedmc_clock_gating_wa()
380 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)  in mtl_pipedmc_clock_gating_wa()  argument
387 	intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,  in mtl_pipedmc_clock_gating_wa()
391 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)  in pipedmc_clock_gating_wa()  argument
393 	if (DISPLAY_VER(i915) >= 14 && enable)  in pipedmc_clock_gating_wa()
394 		mtl_pipedmc_clock_gating_wa(i915);  in pipedmc_clock_gating_wa()
395 	else if (DISPLAY_VER(i915) == 13)  in pipedmc_clock_gating_wa()
396 		adlp_pipedmc_clock_gating_wa(i915, enable);  in pipedmc_clock_gating_wa()
399 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)  in intel_dmc_enable_pipe()  argument
403 	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))  in intel_dmc_enable_pipe()
406 	if (DISPLAY_VER(i915) >= 14)  in intel_dmc_enable_pipe()
407 		intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));  in intel_dmc_enable_pipe()
409 		intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);  in intel_dmc_enable_pipe()
412 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)  in intel_dmc_disable_pipe()  argument
416 	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id))  in intel_dmc_disable_pipe()
419 	if (DISPLAY_VER(i915) >= 14)  in intel_dmc_disable_pipe()
420 		intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);  in intel_dmc_disable_pipe()
422 		intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);  in intel_dmc_disable_pipe()
425 static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,  in is_dmc_evt_ctl_reg()  argument
429 	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));  in is_dmc_evt_ctl_reg()
430 	u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));  in is_dmc_evt_ctl_reg()
435 static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915,  in is_dmc_evt_htp_reg()  argument
439 	u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0));  in is_dmc_evt_htp_reg()
440 	u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));  in is_dmc_evt_htp_reg()
445 static bool disable_dmc_evt(struct drm_i915_private *i915,  in disable_dmc_evt()  argument
449 	if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))  in disable_dmc_evt()
457 	if (IS_TIGERLAKE(i915) &&  in disable_dmc_evt()
462 	if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) &&  in disable_dmc_evt()
469 static u32 dmc_mmiodata(struct drm_i915_private *i915,  in dmc_mmiodata()  argument
473 	if (disable_dmc_evt(i915, dmc_id,  in dmc_mmiodata()
486  * @i915: i915 drm device.
492 void intel_dmc_load_program(struct drm_i915_private *i915)  in intel_dmc_load_program()  argument
494 	struct i915_power_domains *power_domains = &i915->display.power.domains;  in intel_dmc_load_program()
495 	struct intel_dmc *dmc = i915_to_dmc(i915);  in intel_dmc_load_program()
499 	if (!intel_dmc_has_payload(i915))  in intel_dmc_load_program()
502 	pipedmc_clock_gating_wa(i915, true);  in intel_dmc_load_program()
504 	disable_all_event_handlers(i915);  in intel_dmc_load_program()
506 	assert_rpm_wakelock_held(&i915->runtime_pm);  in intel_dmc_load_program()
512 			intel_de_write_fw(i915,  in intel_dmc_load_program()
522 			intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],  in intel_dmc_load_program()
523 				       dmc_mmiodata(i915, dmc, dmc_id, i));  in intel_dmc_load_program()
529 	gen9_set_dc_state_debugmask(i915);  in intel_dmc_load_program()
531 	pipedmc_clock_gating_wa(i915, false);  in intel_dmc_load_program()
536  * @i915: i915 drm device
541 void intel_dmc_disable_program(struct drm_i915_private *i915)  in intel_dmc_disable_program()  argument
543 	if (!intel_dmc_has_payload(i915))  in intel_dmc_disable_program()
546 	pipedmc_clock_gating_wa(i915, true);  in intel_dmc_disable_program()
547 	disable_all_event_handlers(i915);  in intel_dmc_disable_program()
548 	pipedmc_clock_gating_wa(i915, false);  in intel_dmc_disable_program()
551 void assert_dmc_loaded(struct drm_i915_private *i915)  in assert_dmc_loaded()  argument
553 	struct intel_dmc *dmc = i915_to_dmc(i915);  in assert_dmc_loaded()
555 	drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n");  in assert_dmc_loaded()
556 	drm_WARN_ONCE(&i915->drm, dmc &&  in assert_dmc_loaded()
557 		      !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),  in assert_dmc_loaded()
559 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),  in assert_dmc_loaded()
561 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),  in assert_dmc_loaded()
592 	struct drm_i915_private *i915 = dmc->i915;  in dmc_set_fw_offset()  local
600 			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id);  in dmc_set_fw_offset()
622 	struct drm_i915_private *i915 = dmc->i915;  in dmc_mmio_addr_sanity_check()  local
632 	} else if (DISPLAY_VER(i915) >= 13) {  in dmc_mmio_addr_sanity_check()
635 	} else if (DISPLAY_VER(i915) >= 12) {  in dmc_mmio_addr_sanity_check()
639 		drm_warn(&i915->drm, "Unknown mmio range for sanity check");  in dmc_mmio_addr_sanity_check()
655 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_header()  local
703 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",  in parse_dmc_fw_header()
709 		drm_err(&i915->drm, "DMC firmware has wrong dmc header length "  in parse_dmc_fw_header()
716 		drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);  in parse_dmc_fw_header()
722 		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");  in parse_dmc_fw_header()
726 	drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id);  in parse_dmc_fw_header()
731 		drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",  in parse_dmc_fw_header()
733 			    is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :  in parse_dmc_fw_header()
734 			    is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",  in parse_dmc_fw_header()
735 			    disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i],  in parse_dmc_fw_header()
749 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);  in parse_dmc_fw_header()
764 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_header()
774 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_package()  local
787 		drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",  in parse_dmc_fw_package()
801 		drm_err(&i915->drm, "DMC firmware has wrong package header length "  in parse_dmc_fw_package()
819 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_package()
828 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_css()  local
831 		drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_css()
837 		drm_err(&i915->drm, "DMC firmware has wrong CSS header length "  in parse_dmc_fw_css()
850 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw()  local
855 	const struct stepping_info *si = intel_get_stepping_info(i915, &display_info);  in parse_dmc_fw()
885 			drm_err(&i915->drm, "Reading beyond the fw_size\n");  in parse_dmc_fw()
894 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915)  in intel_dmc_runtime_pm_get()  argument
896 	drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);  in intel_dmc_runtime_pm_get()
897 	i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);  in intel_dmc_runtime_pm_get()
900 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915)  in intel_dmc_runtime_pm_put()  argument
903 		fetch_and_zero(&i915->display.dmc.wakeref);  in intel_dmc_runtime_pm_put()
905 	intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);  in intel_dmc_runtime_pm_put()
908 static const char *dmc_fallback_path(struct drm_i915_private *i915)  in dmc_fallback_path()  argument
910 	if (IS_ALDERLAKE_P(i915))  in dmc_fallback_path()
919 	struct drm_i915_private *i915 = dmc->i915;  in dmc_load_work_fn()  local
924 	err = request_firmware(&fw, dmc->fw_path, i915->drm.dev);  in dmc_load_work_fn()
926 	if (err == -ENOENT && !i915->params.dmc_firmware_path) {  in dmc_load_work_fn()
927 		fallback_path = dmc_fallback_path(i915);  in dmc_load_work_fn()
929 			drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n",  in dmc_load_work_fn()
931 			err = request_firmware(&fw, fallback_path, i915->drm.dev);  in dmc_load_work_fn()
939 	if (intel_dmc_has_payload(i915)) {  in dmc_load_work_fn()
940 		intel_dmc_load_program(i915);  in dmc_load_work_fn()
941 		intel_dmc_runtime_pm_put(i915);  in dmc_load_work_fn()
943 		drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n",  in dmc_load_work_fn()
947 		drm_notice(&i915->drm,  in dmc_load_work_fn()
951 		drm_notice(&i915->drm, "DMC firmware homepage: %s",  in dmc_load_work_fn()
960  * @i915: i915 drm device.
965 void intel_dmc_init(struct drm_i915_private *i915)  in intel_dmc_init()  argument
969 	if (!HAS_DMC(i915))  in intel_dmc_init()
980 	intel_dmc_runtime_pm_get(i915);  in intel_dmc_init()
986 	dmc->i915 = i915;  in intel_dmc_init()
990 	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {  in intel_dmc_init()
993 	} else if (IS_DG2(i915)) {  in intel_dmc_init()
996 	} else if (IS_ALDERLAKE_P(i915)) {  in intel_dmc_init()
999 	} else if (IS_ALDERLAKE_S(i915)) {  in intel_dmc_init()
1002 	} else if (IS_DG1(i915)) {  in intel_dmc_init()
1005 	} else if (IS_ROCKETLAKE(i915)) {  in intel_dmc_init()
1008 	} else if (IS_TIGERLAKE(i915)) {  in intel_dmc_init()
1011 	} else if (DISPLAY_VER(i915) == 11) {  in intel_dmc_init()
1014 	} else if (IS_GEMINILAKE(i915)) {  in intel_dmc_init()
1017 	} else if (IS_KABYLAKE(i915) ||  in intel_dmc_init()
1018 		   IS_COFFEELAKE(i915) ||  in intel_dmc_init()
1019 		   IS_COMETLAKE(i915)) {  in intel_dmc_init()
1022 	} else if (IS_SKYLAKE(i915)) {  in intel_dmc_init()
1025 	} else if (IS_BROXTON(i915)) {  in intel_dmc_init()
1030 	if (i915->params.dmc_firmware_path) {  in intel_dmc_init()
1031 		if (strlen(i915->params.dmc_firmware_path) == 0) {  in intel_dmc_init()
1032 			drm_info(&i915->drm,  in intel_dmc_init()
1037 		dmc->fw_path = i915->params.dmc_firmware_path;  in intel_dmc_init()
1041 		drm_dbg_kms(&i915->drm,  in intel_dmc_init()
1046 	i915->display.dmc.dmc = dmc;  in intel_dmc_init()
1048 	drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path);  in intel_dmc_init()
1049 	queue_work(i915->unordered_wq, &dmc->work);  in intel_dmc_init()
1059  * @i915: i915 drm device
1065 void intel_dmc_suspend(struct drm_i915_private *i915)  in intel_dmc_suspend()  argument
1067 	struct intel_dmc *dmc = i915_to_dmc(i915);  in intel_dmc_suspend()
1069 	if (!HAS_DMC(i915))  in intel_dmc_suspend()
1076 	if (!intel_dmc_has_payload(i915))  in intel_dmc_suspend()
1077 		intel_dmc_runtime_pm_put(i915);  in intel_dmc_suspend()
1082  * @i915: i915 drm device
1087 void intel_dmc_resume(struct drm_i915_private *i915)  in intel_dmc_resume()  argument
1089 	if (!HAS_DMC(i915))  in intel_dmc_resume()
1096 	if (!intel_dmc_has_payload(i915))  in intel_dmc_resume()
1097 		intel_dmc_runtime_pm_get(i915);  in intel_dmc_resume()
1102  * @i915: i915 drm device.
1107 void intel_dmc_fini(struct drm_i915_private *i915)  in intel_dmc_fini()  argument
1109 	struct intel_dmc *dmc = i915_to_dmc(i915);  in intel_dmc_fini()
1112 	if (!HAS_DMC(i915))  in intel_dmc_fini()
1115 	intel_dmc_suspend(i915);  in intel_dmc_fini()
1116 	drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);  in intel_dmc_fini()
1123 		i915->display.dmc.dmc = NULL;  in intel_dmc_fini()
1128 				 struct drm_i915_private *i915)  in intel_dmc_print_error_state()  argument
1130 	struct intel_dmc *dmc = i915_to_dmc(i915);  in intel_dmc_print_error_state()
1132 	if (!HAS_DMC(i915))  in intel_dmc_print_error_state()
1137 			  str_yes_no(intel_dmc_has_payload(i915)));  in intel_dmc_print_error_state()
1146 	struct drm_i915_private *i915 = m->private;  in intel_dmc_debugfs_status_show()  local
1147 	struct intel_dmc *dmc = i915_to_dmc(i915);  in intel_dmc_debugfs_status_show()
1151 	if (!HAS_DMC(i915))  in intel_dmc_debugfs_status_show()
1154 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);  in intel_dmc_debugfs_status_show()
1158 		   str_yes_no(intel_dmc_has_payload(i915)));  in intel_dmc_debugfs_status_show()
1161 		   str_yes_no(GRAPHICS_VER(i915) >= 12));  in intel_dmc_debugfs_status_show()
1163 		   str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA)));  in intel_dmc_debugfs_status_show()
1165 		   str_yes_no(IS_ALDERLAKE_P(i915) ||  in intel_dmc_debugfs_status_show()
1166 			      DISPLAY_VER(i915) >= 14));  in intel_dmc_debugfs_status_show()
1168 		   str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB)));  in intel_dmc_debugfs_status_show()
1170 	if (!intel_dmc_has_payload(i915))  in intel_dmc_debugfs_status_show()
1176 	if (DISPLAY_VER(i915) >= 12) {  in intel_dmc_debugfs_status_show()
1179 		if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) {  in intel_dmc_debugfs_status_show()
1189 			   intel_de_read(i915, dc3co_reg));  in intel_dmc_debugfs_status_show()
1191 		dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :  in intel_dmc_debugfs_status_show()
1193 		if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))  in intel_dmc_debugfs_status_show()
1197 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));  in intel_dmc_debugfs_status_show()
1200 			   intel_de_read(i915, dc6_reg));  in intel_dmc_debugfs_status_show()
1203 		   intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));  in intel_dmc_debugfs_status_show()
1207 		   intel_de_read(i915, DMC_SSP_BASE));  in intel_dmc_debugfs_status_show()
1208 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));  in intel_dmc_debugfs_status_show()
1210 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);  in intel_dmc_debugfs_status_show()
1217 void intel_dmc_debugfs_register(struct drm_i915_private *i915)  in intel_dmc_debugfs_register()  argument
1219 	struct drm_minor *minor = i915->drm.primary;  in intel_dmc_debugfs_register()
1222 			    i915, &intel_dmc_debugfs_status_fops);  in intel_dmc_debugfs_register()