Lines Matching full:pipe
26 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
28 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_handle_vblank()
101 * bdw_update_pipe_irq - update DE pipe interrupt
103 * @pipe: pipe whose interrupt to update
108 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
120 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
124 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
125 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
126 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
127 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
132 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
134 bdw_update_pipe_irq(i915, pipe, bits, bits); in bdw_enable_pipe_irq()
138 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
140 bdw_update_pipe_irq(i915, pipe, bits, 0); in bdw_disable_pipe_irq()
180 enum pipe pipe) in i915_pipestat_enable_mask() argument
182 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
191 * On pipe A we don't support the PSR interrupt yet, in i915_pipestat_enable_mask()
192 * on pipe B and C the same bit MBZ. in i915_pipestat_enable_mask()
198 * On pipe B and C we don't support the PSR interrupt yet, on pipe in i915_pipestat_enable_mask()
217 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", in i915_pipestat_enable_mask()
218 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
224 enum pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
226 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
230 "pipe %c: status_mask=0x%x\n", in i915_enable_pipestat()
231 pipe_name(pipe), status_mask); in i915_enable_pipestat()
236 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
239 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
240 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_enable_pipestat()
247 enum pipe pipe, u32 status_mask) in i915_disable_pipestat() argument
249 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
253 "pipe %c: status_mask=0x%x\n", in i915_disable_pipestat()
254 pipe_name(pipe), status_mask); in i915_disable_pipestat()
259 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
262 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
263 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_disable_pipestat()
298 enum pipe pipe, in display_pipe_crc_irq_handler() argument
303 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in display_pipe_crc_irq_handler()
333 enum pipe pipe, in display_pipe_crc_irq_handler() argument
340 enum pipe pipe) in flip_done_handler() argument
342 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe); in flip_done_handler()
355 enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
357 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
363 enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
365 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
366 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
367 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
368 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
369 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
370 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
374 enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
379 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
384 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
388 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
389 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
390 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
391 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
397 enum pipe pipe; in i9xx_pipestat_irq_reset() local
399 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
400 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
404 dev_priv->pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
411 enum pipe pipe; in i9xx_pipestat_irq_ack() local
420 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
435 switch (pipe) { in i9xx_pipestat_irq_ack()
448 status_mask |= dev_priv->pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
453 reg = PIPESTAT(pipe); in i9xx_pipestat_irq_ack()
454 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
455 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_pipestat_irq_ack()
458 * Clear the PIPE*STAT regs before the IIR in i9xx_pipestat_irq_ack()
461 * edge in the ISR pipe event bit if we don't clear in i9xx_pipestat_irq_ack()
466 if (pipe_stats[pipe]) { in i9xx_pipestat_irq_ack()
467 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
477 enum pipe pipe; in i8xx_pipestat_irq_handler() local
479 for_each_pipe(dev_priv, pipe) { in i8xx_pipestat_irq_handler()
480 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i8xx_pipestat_irq_handler()
481 intel_handle_vblank(dev_priv, pipe); in i8xx_pipestat_irq_handler()
483 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i8xx_pipestat_irq_handler()
484 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_pipestat_irq_handler()
487 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
495 enum pipe pipe; in i915_pipestat_irq_handler() local
497 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
498 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
499 intel_handle_vblank(dev_priv, pipe); in i915_pipestat_irq_handler()
501 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_pipestat_irq_handler()
504 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
505 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
507 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_pipestat_irq_handler()
508 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
519 enum pipe pipe; in i965_pipestat_irq_handler() local
521 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
522 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
523 intel_handle_vblank(dev_priv, pipe); in i965_pipestat_irq_handler()
525 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_pipestat_irq_handler()
528 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
529 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
531 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_pipestat_irq_handler()
532 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
545 enum pipe pipe; in valleyview_pipestat_irq_handler() local
547 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
548 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
549 intel_handle_vblank(dev_priv, pipe); in valleyview_pipestat_irq_handler()
551 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) in valleyview_pipestat_irq_handler()
552 flip_done_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
554 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
555 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
557 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
558 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
567 enum pipe pipe; in ibx_irq_handler() local
595 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
596 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
597 pipe_name(pipe), in ibx_irq_handler()
598 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
618 enum pipe pipe; in ivb_err_int_handler() local
623 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
624 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
625 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
627 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
629 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
631 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
641 enum pipe pipe; in cpt_serr_int_handler() local
646 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
647 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) in cpt_serr_int_handler()
648 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); in cpt_serr_int_handler()
655 enum pipe pipe; in cpt_irq_handler() local
680 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
681 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
682 pipe_name(pipe), in cpt_irq_handler()
683 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
692 enum pipe pipe; in ilk_display_irq_handler() local
707 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
708 if (de_iir & DE_PIPE_VBLANK(pipe)) in ilk_display_irq_handler()
709 intel_handle_vblank(dev_priv, pipe); in ilk_display_irq_handler()
711 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) in ilk_display_irq_handler()
712 flip_done_handler(dev_priv, pipe); in ilk_display_irq_handler()
714 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
715 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
717 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
718 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
740 enum pipe pipe; in ivb_display_irq_handler() local
769 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
770 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) in ivb_display_irq_handler()
771 intel_handle_vblank(dev_priv, pipe); in ivb_display_irq_handler()
773 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) in ivb_display_irq_handler()
774 flip_done_handler(dev_priv, pipe); in ivb_display_irq_handler()
902 enum pipe pipe = INVALID_PIPE; in gen11_dsi_te_interrupt_handler() local
931 /* Get PIPE for handling VBLANK event */ in gen11_dsi_te_interrupt_handler()
935 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
938 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
941 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
944 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
948 intel_handle_vblank(dev_priv, pipe); in gen11_dsi_te_interrupt_handler()
1005 enum pipe pipe; in gen8_de_irq_handler() local
1083 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
1086 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_de_irq_handler()
1089 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
1092 "The master control interrupt lied (DE PIPE)!\n"); in gen8_de_irq_handler()
1096 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
1099 intel_handle_vblank(dev_priv, pipe); in gen8_de_irq_handler()
1102 flip_done_handler(dev_priv, pipe); in gen8_de_irq_handler()
1105 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1108 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1113 "Fault errors on pipe %c: 0x%08x\n", in gen8_de_irq_handler()
1114 pipe_name(pipe), in gen8_de_irq_handler()
1189 * we use as a pipe index
1194 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank() local
1198 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
1223 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank() local
1227 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
1237 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank() local
1240 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_enable_vblank()
1283 enum pipe pipe = crtc->pipe; in bdw_enable_vblank() local
1290 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_enable_vblank()
1303 * we use as a pipe index
1308 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank() local
1312 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
1329 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank() local
1333 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
1341 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank() local
1344 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_disable_vblank()
1355 enum pipe pipe = crtc->pipe; in bdw_disable_vblank() local
1362 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_disable_vblank()
1390 enum pipe pipe; in vlv_display_irq_postinstall() local
1395 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
1396 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
1418 enum pipe pipe; in gen8_display_irq_reset() local
1426 for_each_pipe(dev_priv, pipe) in gen8_display_irq_reset()
1428 POWER_DOMAIN_PIPE(pipe))) in gen8_display_irq_reset()
1429 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_display_irq_reset()
1438 enum pipe pipe; in gen11_display_irq_reset() local
1465 for_each_pipe(dev_priv, pipe) in gen11_display_irq_reset()
1467 POWER_DOMAIN_PIPE(pipe))) in gen11_display_irq_reset()
1468 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen11_display_irq_reset()
1489 enum pipe pipe; in gen8_irq_power_well_post_enable() local
1498 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
1499 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_irq_power_well_post_enable()
1500 dev_priv->de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
1501 ~dev_priv->de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
1510 enum pipe pipe; in gen8_irq_power_well_pre_disable() local
1519 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
1520 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_irq_power_well_pre_disable()
1641 enum pipe pipe; in gen8_de_irq_postinstall() local
1696 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
1697 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
1700 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
1701 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_de_irq_postinstall()
1702 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()