35 #define HAS_4TILE(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)  argument
36 #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)  argument
37 #define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)->has_cdclk_crawl)  argument
38 #define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)->has_cdclk_squash)  argument
39 #define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))  argument
40 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))  argument
41 #define HAS_DDI(i915)			(DISPLAY_INFO(i915)->has_ddi)  argument
42 #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)  argument
43 #define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)  argument
44 #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))  argument
45 #define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)  argument
46 #define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)  argument
47 #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)  argument
48 #define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)  argument
50 #define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)  argument
51 #define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)  argument
52 #define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)  argument
53 #define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) >= 4)  argument
54 #define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))  argument
55 #define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)  argument
56 #define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))  argument
57 #define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)  argument
58 #define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))  argument
59 #define HAS_LRR(i915)			(DISPLAY_VER(i915) >= 12)  argument
60 #define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))  argument
61 #define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)  argument
62 #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)  argument
63 #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)  argument
64 #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)  argument
65 #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)  argument
66 #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)  argument
67 #define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))  argument
68 #define HAS_TRANSCODER(i915, trans)	((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \  argument
70 #define HAS_VRR(i915)			(DISPLAY_VER(i915) >= 11)  argument
71 #define INTEL_NUM_PIPES(i915)		(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))  argument
72 #define I915_HAS_HOTPLUG(i915)		(DISPLAY_INFO(i915)->has_hotplug)  argument
73 #define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)  argument
74 #define SUPPORTS_TV(i915)		(DISPLAY_INFO(i915)->supports_tv)  argument
91  *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
92  *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
101 #define DISPLAY_INFO(i915)		((i915)->display.info.__device_info)  argument
102 #define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->display.info.__runtime_info)  argument
104 #define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)  argument
105 #define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \  argument
106 				       DISPLAY_RUNTIME_INFO(i915)->ip.rel)
107 #define IS_DISPLAY_VER(i915, from, until) \  argument
108 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
162 bool intel_display_device_enabled(struct drm_i915_private *i915);
163 void intel_display_device_probe(struct drm_i915_private *i915);
164 void intel_display_device_remove(struct drm_i915_private *i915);
165 void intel_display_device_info_runtime_init(struct drm_i915_private *i915);