Lines Matching +full:- +full:bit
1 // SPDX-License-Identifier: MIT
184 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
186 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
197 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
198 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
203 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
209 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
215 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
216 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
222 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
223 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
233 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
235 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
236 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
252 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
271 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
294 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
296 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
302 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
310 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
311 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
317 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
324 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
325 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
335 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
337 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
338 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
347 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
357 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
359 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
360 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
361 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
371 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
373 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
374 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
375 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
387 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
389 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
390 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
405 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
407 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
408 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
409 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
410 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
425 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
427 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
428 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
429 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
430 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
442 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
444 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
445 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
449 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
450 .dbuf.slice_mask = BIT(DBUF_S1),
465 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
467 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
468 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
469 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
470 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
474 .dbuf.slice_mask = BIT(DBUF_S1), \
488 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
489 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
491 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
492 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
493 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
494 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
498 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
505 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
512 .abox_mask = BIT(0), \
514 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
545 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
547 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
548 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
549 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
550 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
555 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
561 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
567 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
600 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
602 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
603 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
604 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
605 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
614 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
615 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
621 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
622 BIT(PORT_TC1) | BIT(PORT_TC2),
627 .abox_mask = BIT(0),
631 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
633 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
634 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
635 BIT(PORT_TC1) | BIT(PORT_TC2),
643 .__runtime_defaults.port_mask = BIT(PORT_A) |
644 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
655 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
656 BIT(DBUF_S4), \
685 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
688 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
696 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
697 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
698 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
699 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
700 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
708 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
709 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
710 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
711 BIT(PORT_TC1),
722 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
723 BIT(DBUF_S4), \
748 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
749 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
750 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
755 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
756 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
757 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
767 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
768 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
838 * Do not add any GMD_ID-based platforms to this list. They will
856 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in probe_gmdid_display()
872 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); in probe_gmdid_display()
880 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); in probe_gmdid_display()
893 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", in probe_gmdid_display()
901 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in probe_display()
905 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); in probe_display()
910 if (intel_display_ids[i].devid == pdev->device) in probe_display()
914 drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", in probe_display()
915 pdev->device); in probe_display()
933 &DISPLAY_INFO(i915)->__runtime_defaults, in intel_display_device_probe()
937 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; in intel_display_device_probe()
938 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; in intel_display_device_probe()
939 DISPLAY_RUNTIME_INFO(i915)->ip.step = step; in intel_display_device_probe()
942 intel_display_params_copy(&i915->display.params); in intel_display_device_probe()
947 intel_display_params_free(&i915->display.params); in intel_display_device_remove()
955 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in __intel_display_device_info_runtime_init()
956 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); in __intel_display_device_info_runtime_init()
957 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); in __intel_display_device_info_runtime_init()
961 display_runtime->port_mask &= ~BIT(PORT_D); in __intel_display_device_info_runtime_init()
964 display_runtime->port_mask |= BIT(PORT_F); in __intel_display_device_info_runtime_init()
966 /* Wa_14011765242: adl-s A0,A1 */ in __intel_display_device_info_runtime_init()
969 display_runtime->num_scalers[pipe] = 0; in __intel_display_device_info_runtime_init()
972 display_runtime->num_scalers[pipe] = 2; in __intel_display_device_info_runtime_init()
974 display_runtime->num_scalers[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
975 display_runtime->num_scalers[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
976 display_runtime->num_scalers[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
981 display_runtime->num_sprites[pipe] = 4; in __intel_display_device_info_runtime_init()
984 display_runtime->num_sprites[pipe] = 6; in __intel_display_device_info_runtime_init()
987 display_runtime->num_sprites[pipe] = 3; in __intel_display_device_info_runtime_init()
998 display_runtime->num_sprites[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
999 display_runtime->num_sprites[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1000 display_runtime->num_sprites[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1003 display_runtime->num_sprites[pipe] = 2; in __intel_display_device_info_runtime_init()
1006 display_runtime->num_sprites[pipe] = 1; in __intel_display_device_info_runtime_init()
1011 drm_info(&i915->drm, "Display not present, disabling\n"); in __intel_display_device_info_runtime_init()
1020 * SFUSE_STRAP is supposed to have a bit signalling the display in __intel_display_device_info_runtime_init()
1032 drm_info(&i915->drm, in __intel_display_device_info_runtime_init()
1036 drm_info(&i915->drm, "PipeC fused off\n"); in __intel_display_device_info_runtime_init()
1037 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1038 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1044 display_runtime->pipe_mask &= ~BIT(PIPE_A); in __intel_display_device_info_runtime_init()
1045 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); in __intel_display_device_info_runtime_init()
1046 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); in __intel_display_device_info_runtime_init()
1049 display_runtime->pipe_mask &= ~BIT(PIPE_B); in __intel_display_device_info_runtime_init()
1050 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); in __intel_display_device_info_runtime_init()
1051 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); in __intel_display_device_info_runtime_init()
1054 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1055 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1056 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); in __intel_display_device_info_runtime_init()
1061 display_runtime->pipe_mask &= ~BIT(PIPE_D); in __intel_display_device_info_runtime_init()
1062 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); in __intel_display_device_info_runtime_init()
1063 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); in __intel_display_device_info_runtime_init()
1066 if (!display_runtime->pipe_mask) in __intel_display_device_info_runtime_init()
1070 display_runtime->has_hdcp = 0; in __intel_display_device_info_runtime_init()
1073 display_runtime->fbc_mask = 0; in __intel_display_device_info_runtime_init()
1076 display_runtime->has_dmc = 0; in __intel_display_device_info_runtime_init()
1080 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1088 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1093 if (display_runtime->num_scalers[pipe]) in __intel_display_device_info_runtime_init()
1094 display_runtime->num_scalers[pipe] = 1; in __intel_display_device_info_runtime_init()
1111 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); in intel_display_device_info_runtime_init()
1112 i915->display.info.__device_info = &no_display; in intel_display_device_info_runtime_init()
1115 /* Disable nuclear pageflip by default on pre-g4x */ in intel_display_device_info_runtime_init()
1116 if (!i915->display.params.nuclear_pageflip && in intel_display_device_info_runtime_init()
1118 i915->drm.driver_features &= ~DRIVER_ATOMIC; in intel_display_device_info_runtime_init()
1125 if (runtime->ip.rel) in intel_display_device_info_print()
1127 runtime->ip.ver, in intel_display_device_info_print()
1128 runtime->ip.rel); in intel_display_device_info_print()
1131 runtime->ip.ver); in intel_display_device_info_print()
1133 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) in intel_display_device_info_print()
1137 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); in intel_display_device_info_print()
1138 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); in intel_display_device_info_print()
1139 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); in intel_display_device_info_print()
1154 drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); in intel_display_device_enabled()
1156 return !i915->display.params.disable_display && in intel_display_device_enabled()