2  * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
151 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=  in vlv_get_cck_clock()
155 	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);  in vlv_get_cck_clock()
165 	if (dev_priv->hpll_freq == 0)  in vlv_get_cck_clock_hpll()
166 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);  in vlv_get_cck_clock_hpll()
168 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);  in vlv_get_cck_clock_hpll()
180 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",  in intel_update_czclk()
183 	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",  in intel_update_czclk()
184 		dev_priv->czclk_freq);  in intel_update_czclk()
189 	return (crtc_state->active_planes &  in is_hdr_mode()
225 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
231 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
243 	return ffs(crtc_state->bigjoiner_pipes) - 1;  in bigjoiner_master_pipe()
248 	if (crtc_state->bigjoiner_pipes)  in intel_crtc_bigjoiner_slave_pipes()
249 		return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));  in intel_crtc_bigjoiner_slave_pipes()
256 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_slave()
258 	return crtc_state->bigjoiner_pipes &&  in intel_crtc_is_bigjoiner_slave()
259 		crtc->pipe != bigjoiner_master_pipe(crtc_state);  in intel_crtc_is_bigjoiner_slave()
264 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_master()
266 	return crtc_state->bigjoiner_pipes &&  in intel_crtc_is_bigjoiner_master()
267 		crtc->pipe == bigjoiner_master_pipe(crtc_state);  in intel_crtc_is_bigjoiner_master()
272 	return hweight8(crtc_state->bigjoiner_pipes);  in intel_bigjoiner_num_pipes()
277 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in intel_master_crtc()
282 		return to_intel_crtc(crtc_state->uapi.crtc);  in intel_master_crtc()
288 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
289 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_wait_for_pipe_off()
292 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
297 			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");  in intel_wait_for_pipe_off()
333 	struct drm_i915_private *i915 = to_i915(plane->base.dev);  in assert_plane()
337 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
341 			plane->base.name, str_on_off(state),  in assert_plane()
350 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in assert_planes_disabled()
353 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)  in assert_planes_disabled()
364 	switch (dig_port->base.port) {  in vlv_wait_port_ready()
366 		MISSING_CASE(dig_port->base.port);  in vlv_wait_port_ready()
385 		drm_WARN(&dev_priv->drm, 1,  in vlv_wait_port_ready()
387 			 dig_port->base.base.base.id, dig_port->base.base.name,  in vlv_wait_port_ready()
394 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_transcoder()
395 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_enable_transcoder()
396 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_transcoder()
397 	enum pipe pipe = crtc->pipe;  in intel_enable_transcoder()
400 	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_transcoder()
415 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_transcoder()
425 	/* Wa_22012358565:adl-p */  in intel_enable_transcoder()
433 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));  in intel_enable_transcoder()
454 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_transcoder()
455 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_disable_transcoder()
456 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_transcoder()
457 	enum pipe pipe = crtc->pipe;  in intel_disable_transcoder()
460 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_transcoder()
476 	if (old_crtc_state->double_wide)  in intel_disable_transcoder()
498 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)  in intel_rotation_info_size()
499 		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;  in intel_rotation_info_size()
509 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {  in intel_remapped_info_size()
512 		if (rem_info->plane[i].linear)  in intel_remapped_info_size()
513 			plane_size = rem_info->plane[i].size;  in intel_remapped_info_size()
515 			plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;  in intel_remapped_info_size()
520 		if (rem_info->plane_alignment)  in intel_remapped_info_size()
521 			size = ALIGN(size, rem_info->plane_alignment);  in intel_remapped_info_size()
531 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_uses_fence()
532 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_plane_uses_fence()
535 		(plane->fbc &&  in intel_plane_uses_fence()
536 		 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);  in intel_plane_uses_fence()
542  * offset is only used with linear buffers on pre-hsw and tiled buffers
549 	const struct drm_framebuffer *fb = state->hw.fb;  in intel_fb_xy_to_linear()
550 	unsigned int cpp = fb->format->cpp[color_plane];  in intel_fb_xy_to_linear()
551 	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;  in intel_fb_xy_to_linear()
557  * Add the x/y offsets derived from fb->offsets[] to the user
566 	*x += state->view.color_plane[color_plane].x;  in intel_add_fb_offsets()
567 	*y += state->view.color_plane[color_plane].y;  in intel_add_fb_offsets()
588 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
590 	return plane->max_stride(plane, pixel_format, modifier,  in intel_plane_fb_max_stride()
598 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
600 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
603 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
605 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
610 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_plane_fixup_bitmasks()
618 	crtc_state->enabled_planes = 0;  in intel_plane_fixup_bitmasks()
619 	crtc_state->active_planes = 0;  in intel_plane_fixup_bitmasks()
621 	drm_for_each_plane_mask(plane, &dev_priv->drm,  in intel_plane_fixup_bitmasks()
622 				crtc_state->uapi.plane_mask) {  in intel_plane_fixup_bitmasks()
623 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
624 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
631 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_disable_noatomic()
633 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
635 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
637 	drm_dbg_kms(&dev_priv->drm,  in intel_plane_disable_noatomic()
639 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
640 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
644 	crtc_state->data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
645 	crtc_state->data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
646 	crtc_state->rel_data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
647 	crtc_state->rel_data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
648 	crtc_state->min_cdclk[plane->id] = 0;  in intel_plane_disable_noatomic()
650 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&  in intel_plane_disable_noatomic()
652 		crtc_state->ips_enabled = false;  in intel_plane_disable_noatomic()
658 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
660 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
663 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
673 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
674 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);  in intel_plane_disable_noatomic()
686 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
693 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
694 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_set_pipe_chicken()
695 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
703 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
708 	 * Set the pixel rounding bit to 1 for allowing  in icl_set_pipe_chicken()
735 	drm_for_each_crtc(crtc, &dev_priv->drm) {  in intel_has_pending_fb_unpin()
737 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
738 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
741 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
742 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
772 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
773 		if (connector_state->crtc != &master_crtc->base)  in intel_get_crtc_new_encoder()
776 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
780 	drm_WARN(state->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
782 		 num_encoders, pipe_name(master_crtc->pipe));  in intel_get_crtc_new_encoder()
789 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pfit_enable()
790 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_enable()
791 	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;  in ilk_pfit_enable()
792 	enum pipe pipe = crtc->pipe;  in ilk_pfit_enable()
795 	int x = dst->x1;  in ilk_pfit_enable()
796 	int y = dst->y1;  in ilk_pfit_enable()
798 	if (!crtc_state->pch_pfit.enabled)  in ilk_pfit_enable()
801 	/* Force use of hard-coded filter coefficients  in ilk_pfit_enable()
802 	 * as some pre-programmed values are broken,  in ilk_pfit_enable()
819 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
820 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
829 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_nv12_wa()
831 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
843 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_scalerclk_wa()
846 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)  in needs_scalerclk_wa()
854 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_cursorclk_wa()
858 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&  in needs_cursorclk_wa()
886 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in needs_async_flip_vtd_wa()
888 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&  in needs_async_flip_vtd_wa()
901 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_audio_enable()
903 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_audio_enable()
905 		if (conn_state->crtc != &crtc->base)  in intel_encoders_audio_enable()
908 		if (encoder->audio_enable)  in intel_encoders_audio_enable()
909 			encoder->audio_enable(encoder, crtc_state, conn_state);  in intel_encoders_audio_enable()
922 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_audio_disable()
924 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_audio_disable()
926 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_audio_disable()
929 		if (encoder->audio_disable)  in intel_encoders_audio_disable()
930 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);  in intel_encoders_audio_disable()
935 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
936 	 (new_crtc_state)->feature)
938 	((old_crtc_state)->feature && \
939 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
944 	if (!new_crtc_state->hw.active)  in planes_enabling()
953 	if (!old_crtc_state->hw.active)  in planes_disabling()
962 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||  in vrr_params_changed()
963 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||  in vrr_params_changed()
964 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||  in vrr_params_changed()
965 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||  in vrr_params_changed()
966 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;  in vrr_params_changed()
972 	if (!new_crtc_state->hw.active)  in vrr_enabling()
976 		(new_crtc_state->vrr.enable &&  in vrr_enabling()
977 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in vrr_enabling()
984 	if (!old_crtc_state->hw.active)  in vrr_disabling()
988 		(old_crtc_state->vrr.enable &&  in vrr_disabling()
989 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in vrr_disabling()
996 	if (!new_crtc_state->hw.active)  in audio_enabling()
1000 		(new_crtc_state->has_audio &&  in audio_enabling()
1001 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_enabling()
1007 	if (!old_crtc_state->hw.active)  in audio_disabling()
1011 		(old_crtc_state->has_audio &&  in audio_disabling()
1012 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_disabling()
1021 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_post_plane_update()
1026 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
1030 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);  in intel_post_plane_update()
1032 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
1065 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
1071 		if (plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
1072 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
1073 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
1082 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
1088 		if (plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
1089 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
1090 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
1101 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &  in intel_crtc_async_flip_disable_wa()
1102 				       ~new_crtc_state->async_flip_planes;  in intel_crtc_async_flip_disable_wa()
1109 		if (plane->need_async_flip_disable_wa &&  in intel_crtc_async_flip_disable_wa()
1110 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
1111 		    disable_async_flip_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
1116 			plane->async_flip(plane, old_crtc_state,  in intel_crtc_async_flip_disable_wa()
1129 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_pre_plane_update()
1134 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
1175 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
1177 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
1180 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
1182 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1183 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))  in intel_pre_plane_update()
1188 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
1193 	if (old_crtc_state->hw.active &&  in intel_pre_plane_update()
1194 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))  in intel_pre_plane_update()
1199 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
1204 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
1205 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
1206 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
1217 			if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
1236 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)  in intel_pre_plane_update()
1243 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_planes()
1246 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
1255 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
1256 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
1261 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
1262 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
1270 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_encoders_update_prepare()
1276 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.  in intel_encoders_update_prepare()
1277 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.  in intel_encoders_update_prepare()
1279 	if (i915->display.dpll.mgr) {  in intel_encoders_update_prepare()
1284 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;  in intel_encoders_update_prepare()
1285 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;  in intel_encoders_update_prepare()
1299 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
1301 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
1303 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
1306 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
1307 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
1321 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
1323 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
1325 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
1328 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
1329 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
1343 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
1345 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
1347 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
1350 		if (encoder->enable)  in intel_encoders_enable()
1351 			encoder->enable(state, encoder,  in intel_encoders_enable()
1366 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
1368 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
1370 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
1374 		if (encoder->disable)  in intel_encoders_disable()
1375 			encoder->disable(state, encoder,  in intel_encoders_disable()
1389 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
1391 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
1393 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
1396 		if (encoder->post_disable)  in intel_encoders_post_disable()
1397 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
1411 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
1413 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
1415 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
1418 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
1419 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
1433 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
1435 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
1437 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
1440 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
1441 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
1448 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_disable_primary_plane()
1449 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);  in intel_disable_primary_plane()
1451 	plane->disable_arm(plane, crtc_state);  in intel_disable_primary_plane()
1456 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_configure_cpu_transcoder()
1457 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_configure_cpu_transcoder()
1459 	if (crtc_state->has_pch_encoder) {  in ilk_configure_cpu_transcoder()
1461 					       &crtc_state->fdi_m_n);  in ilk_configure_cpu_transcoder()
1464 					       &crtc_state->dp_m_n);  in ilk_configure_cpu_transcoder()
1466 					       &crtc_state->dp_m2_n2);  in ilk_configure_cpu_transcoder()
1479 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_enable()
1480 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
1482 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in ilk_crtc_enable()
1502 	crtc->active = true;  in ilk_crtc_enable()
1506 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1528 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
1544 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1568 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
1569 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_linetime_wm()
1571 	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
1572 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
1573 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
1578 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_frame_start_delay()
1579 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_set_frame_start_delay()
1581 	intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),  in hsw_set_frame_start_delay()
1583 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));  in hsw_set_frame_start_delay()
1592 	 * Enable sequence steps 1-7 on bigjoiner master  in icl_ddi_bigjoiner_pre_enable()
1597 	if (crtc_state->shared_dpll)  in icl_ddi_bigjoiner_pre_enable()
1606 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_configure_cpu_transcoder()
1607 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_configure_cpu_transcoder()
1608 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_configure_cpu_transcoder()
1610 	if (crtc_state->has_pch_encoder) {  in hsw_configure_cpu_transcoder()
1612 					       &crtc_state->fdi_m_n);  in hsw_configure_cpu_transcoder()
1615 					       &crtc_state->dp_m_n);  in hsw_configure_cpu_transcoder()
1617 					       &crtc_state->dp_m2_n2);  in hsw_configure_cpu_transcoder()
1626 			       crtc_state->pixel_multiplier - 1);  in hsw_configure_cpu_transcoder()
1638 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_crtc_enable()
1639 	enum pipe pipe = crtc->pipe, hsw_workaround_pipe;  in hsw_crtc_enable()
1640 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
1643 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in hsw_crtc_enable()
1646 	intel_dmc_enable_pipe(dev_priv, crtc->pipe);  in hsw_crtc_enable()
1648 	if (!new_crtc_state->bigjoiner_pipes) {  in hsw_crtc_enable()
1651 		if (new_crtc_state->shared_dpll)  in hsw_crtc_enable()
1672 	crtc->active = true;  in hsw_crtc_enable()
1676 		new_crtc_state->pch_pfit.enabled;  in hsw_crtc_enable()
1715 	hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
1728 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in ilk_pfit_disable()
1729 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_disable()
1730 	enum pipe pipe = crtc->pipe;  in ilk_pfit_disable()
1734 	if (!old_crtc_state->pch_pfit.enabled)  in ilk_pfit_disable()
1747 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_disable()
1748 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
1766 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1771 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1785 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_crtc_disable()
1789 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
1803 		intel_dmc_disable_pipe(i915, crtc->pipe);  in hsw_crtc_disable()
1805 		for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,  in hsw_crtc_disable()
1807 			intel_dmc_disable_pipe(i915, slave_crtc->pipe);  in hsw_crtc_disable()
1813 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_pfit_enable()
1814 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_enable()
1816 	if (!crtc_state->gmch_pfit.control)  in i9xx_pfit_enable()
1823 	drm_WARN_ON(&dev_priv->drm,  in i9xx_pfit_enable()
1825 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_pfit_enable()
1828 		       crtc_state->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
1829 	intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);  in i9xx_pfit_enable()
1833 	intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);  in i9xx_pfit_enable()
1860 	 * DG2's "TC1", although TC-capable output, doesn't share the same flow  in intel_phy_is_tc()
1889 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
1891 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
1893 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
1895 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
1900 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
1909 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
1911 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
1917 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_aux_power_domain()
1920 		return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
1922 	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
1928 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
1929 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in get_crtc_power_domains()
1930 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
1932 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
1934 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);  in get_crtc_power_domains()
1936 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
1939 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);  in get_crtc_power_domains()
1940 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1941 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
1942 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
1943 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);  in get_crtc_power_domains()
1945 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,  in get_crtc_power_domains()
1946 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
1949 		set_bit(intel_encoder->power_domain, mask->bits);  in get_crtc_power_domains()
1952 	if (HAS_DDI(dev_priv) && crtc_state->has_audio)  in get_crtc_power_domains()
1953 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);  in get_crtc_power_domains()
1955 	if (crtc_state->shared_dpll)  in get_crtc_power_domains()
1956 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);  in get_crtc_power_domains()
1958 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
1959 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1965 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_get_crtc_power_domains()
1966 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_modeset_get_crtc_power_domains()
1974 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
1976 	bitmap_andnot(old_domains->bits,  in intel_modeset_get_crtc_power_domains()
1977 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
1983 					       &crtc->enabled_power_domains,  in intel_modeset_get_crtc_power_domains()
1990 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),  in intel_modeset_put_crtc_power_domains()
1991 					    &crtc->enabled_power_domains,  in intel_modeset_put_crtc_power_domains()
1997 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_configure_cpu_transcoder()
1998 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_configure_cpu_transcoder()
2002 					       &crtc_state->dp_m_n);  in i9xx_configure_cpu_transcoder()
2004 					       &crtc_state->dp_m2_n2);  in i9xx_configure_cpu_transcoder()
2017 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in valleyview_crtc_enable()
2018 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
2020 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in valleyview_crtc_enable()
2034 	crtc->active = true;  in valleyview_crtc_enable()
2068 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_enable()
2069 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
2071 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in i9xx_crtc_enable()
2078 	crtc->active = true;  in i9xx_crtc_enable()
2110 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in i9xx_pfit_disable()
2111 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_disable()
2113 	if (!old_crtc_state->gmch_pfit.control)  in i9xx_pfit_disable()
2116 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);  in i9xx_pfit_disable()
2118 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",  in i9xx_pfit_disable()
2128 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_disable()
2129 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
2162 	if (!dev_priv->display.funcs.wm->initial_watermarks)  in i9xx_crtc_disable()
2180 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_supports_double_wide()
2184 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));  in intel_crtc_supports_double_wide()
2189 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
2193 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
2194 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
2197 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
2201 		      drm_rect_width(&crtc_state->pipe_src) << 16,  in ilk_pipe_pixel_rate()
2202 		      drm_rect_height(&crtc_state->pipe_src) << 16);  in ilk_pipe_pixel_rate()
2204 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
2211 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
2212 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
2213 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
2214 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
2216 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
2217 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
2218 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
2219 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
2221 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
2222 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
2224 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
2231 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_crtc_compute_pixel_rate()
2235 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2236 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
2238 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2250 	mode->crtc_clock /= num_pipes;  in intel_bigjoiner_adjust_timings()
2251 	mode->crtc_hdisplay /= num_pipes;  in intel_bigjoiner_adjust_timings()
2252 	mode->crtc_hblank_start /= num_pipes;  in intel_bigjoiner_adjust_timings()
2253 	mode->crtc_hblank_end /= num_pipes;  in intel_bigjoiner_adjust_timings()
2254 	mode->crtc_hsync_start /= num_pipes;  in intel_bigjoiner_adjust_timings()
2255 	mode->crtc_hsync_end /= num_pipes;  in intel_bigjoiner_adjust_timings()
2256 	mode->crtc_htotal /= num_pipes;  in intel_bigjoiner_adjust_timings()
2262 	int overlap = crtc_state->splitter.pixel_overlap;  in intel_splitter_adjust_timings()
2263 	int n = crtc_state->splitter.link_count;  in intel_splitter_adjust_timings()
2265 	if (!crtc_state->splitter.enable)  in intel_splitter_adjust_timings()
2272 	 * h_full = (h_segment - pixel_overlap) * link_count  in intel_splitter_adjust_timings()
2274 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;  in intel_splitter_adjust_timings()
2275 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;  in intel_splitter_adjust_timings()
2276 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;  in intel_splitter_adjust_timings()
2277 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;  in intel_splitter_adjust_timings()
2278 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;  in intel_splitter_adjust_timings()
2279 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;  in intel_splitter_adjust_timings()
2280 	mode->crtc_clock *= n;  in intel_splitter_adjust_timings()
2285 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()
2286 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
2287 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
2295 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_readout_derived_state()
2308 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *  in intel_crtc_readout_derived_state()
2309 		(intel_bigjoiner_num_pipes(crtc_state) ?: 1);  in intel_crtc_readout_derived_state()
2310 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);  in intel_crtc_readout_derived_state()
2312 	/* Derive per-pipe timings in case bigjoiner is used */  in intel_crtc_readout_derived_state()
2322 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
2335 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_bigjoiner_compute_pipe_src()
2336 	height = drm_rect_height(&crtc_state->pipe_src);  in intel_bigjoiner_compute_pipe_src()
2338 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_bigjoiner_compute_pipe_src()
2344 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_src()
2345 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_src()
2351 	 * - DVO ganged mode  in intel_crtc_compute_pipe_src()
2352 	 * - LVDS dual channel mode  in intel_crtc_compute_pipe_src()
2353 	 * - Double wide pipe  in intel_crtc_compute_pipe_src()
2355 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {  in intel_crtc_compute_pipe_src()
2356 		if (crtc_state->double_wide) {  in intel_crtc_compute_pipe_src()
2357 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2359 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2360 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2365 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2367 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2368 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2377 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_mode()
2378 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_mode()
2379 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_compute_pipe_mode()
2380 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_compute_pipe_mode()
2381 	int clock_limit = i915->max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2389 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_compute_pipe_mode()
2392 	/* Derive per-pipe timings in case bigjoiner is used */  in intel_crtc_compute_pipe_mode()
2397 		clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;  in intel_crtc_compute_pipe_mode()
2404 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2405 			clock_limit = i915->max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2406 			crtc_state->double_wide = true;  in intel_crtc_compute_pipe_mode()
2410 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2411 		drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_mode()
2413 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_pipe_mode()
2414 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_pipe_mode()
2415 			    str_yes_no(crtc_state->double_wide));  in intel_crtc_compute_pipe_mode()
2416 		return -EINVAL;  in intel_crtc_compute_pipe_mode()
2443 	if (crtc_state->has_pch_encoder)  in intel_crtc_compute_config()
2454 		*num >>= 1;  in intel_reduce_m_n_ratio()
2455 		*den >>= 1;  in intel_reduce_m_n_ratio()
2489 	m_n->tu = 64;  in intel_link_compute_m_n()
2490 	compute_m_n(&m_n->data_m, &m_n->data_n,  in intel_link_compute_m_n()
2494 	compute_m_n(&m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
2512 		if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
2513 			drm_dbg_kms(&dev_priv->drm,  in intel_panel_sanitize_ssc()
2516 				    str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
2517 			dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
2526 	m_n->tu = 1;  in intel_zero_m_n()
2534 	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);  in intel_set_m_n()
2535 	intel_de_write(i915, data_n_reg, m_n->data_n);  in intel_set_m_n()
2536 	intel_de_write(i915, link_m_reg, m_n->link_m);  in intel_set_m_n()
2541 	intel_de_write(i915, link_n_reg, m_n->link_n);  in intel_set_m_n()
2557 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m1_n1()
2558 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m1_n1()
2574 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m2_n2()
2586 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
2587 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings()
2588 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
2589 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
2590 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
2596 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings()
2597 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
2598 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings()
2599 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
2601 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
2603 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
2604 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
2607 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
2609 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
2610 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
2612 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
2621 			       crtc_vblank_start - crtc_vdisplay);  in intel_set_transcoder_timings()
2627 		crtc_vblank_start = 1;  in intel_set_transcoder_timings()
2635 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |  in intel_set_transcoder_timings()
2636 		       HTOTAL(adjusted_mode->crtc_htotal - 1));  in intel_set_transcoder_timings()
2638 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |  in intel_set_transcoder_timings()
2639 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));  in intel_set_transcoder_timings()
2641 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |  in intel_set_transcoder_timings()
2642 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));  in intel_set_transcoder_timings()
2645 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2646 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2648 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings()
2649 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings()
2651 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |  in intel_set_transcoder_timings()
2652 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));  in intel_set_transcoder_timings()
2661 			       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2662 			       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2667 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings_lrr()
2668 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings_lrr()
2669 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings_lrr()
2670 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings_lrr()
2673 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings_lrr()
2674 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings_lrr()
2675 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings_lrr()
2676 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings_lrr()
2678 	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);  in intel_set_transcoder_timings_lrr()
2685 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings_lrr()
2686 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings_lrr()
2692 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings_lrr()
2693 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings_lrr()
2698 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
2699 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_pipe_src_size()
2700 	int width = drm_rect_width(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2701 	int height = drm_rect_height(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2702 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
2708 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));  in intel_set_pipe_src_size()
2713 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_pipe_is_interlaced()
2714 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
2729 	struct drm_device *dev = crtc->base.dev;  in intel_get_transcoder_timings()
2731 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
2732 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_get_transcoder_timings()
2736 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2737 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2741 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2742 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2746 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2747 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2750 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2751 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2756 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2757 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2760 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2761 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2764 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
2765 		adjusted_mode->crtc_vtotal += 1;  in intel_get_transcoder_timings()
2766 		adjusted_mode->crtc_vblank_end += 1;  in intel_get_transcoder_timings()
2770 		adjusted_mode->crtc_vblank_start =  in intel_get_transcoder_timings()
2771 			adjusted_mode->crtc_vdisplay +  in intel_get_transcoder_timings()
2777 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_bigjoiner_adjust_pipe_src()
2779 	enum pipe master_pipe, pipe = crtc->pipe;  in intel_bigjoiner_adjust_pipe_src()
2786 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_bigjoiner_adjust_pipe_src()
2788 	drm_rect_translate_to(&crtc_state->pipe_src,  in intel_bigjoiner_adjust_pipe_src()
2789 			      (pipe - master_pipe) * width, 0);  in intel_bigjoiner_adjust_pipe_src()
2795 	struct drm_device *dev = crtc->base.dev;  in intel_get_pipe_src_size()
2799 	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));  in intel_get_pipe_src_size()
2801 	drm_rect_init(&pipe_config->pipe_src, 0, 0,  in intel_get_pipe_src_size()
2802 		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,  in intel_get_pipe_src_size()
2803 		      REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);  in intel_get_pipe_src_size()
2810 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_set_pipeconf()
2811 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_set_pipeconf()
2812 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_set_pipeconf()
2816 	 * - We keep both pipes enabled on 830  in i9xx_set_pipeconf()
2817 	 * - During modeset the pipe is still disabled and must remain so  in i9xx_set_pipeconf()
2818 	 * - During fastset the pipe is already enabled and must remain so  in i9xx_set_pipeconf()
2823 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
2830 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
2834 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
2837 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
2851 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
2862 	     crtc_state->limited_color_range)  in i9xx_set_pipeconf()
2865 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
2867 	if (crtc_state->wgc_enable)  in i9xx_set_pipeconf()
2870 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in i9xx_set_pipeconf()
2887 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_get_pfit_config()
2888 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pfit_config()
2905 	if (pipe != crtc->pipe)  in i9xx_get_pfit_config()
2908 	crtc_state->gmch_pfit.control = tmp;  in i9xx_get_pfit_config()
2909 	crtc_state->gmch_pfit.pgm_ratios =  in i9xx_get_pfit_config()
2916 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_output_format()
2919 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_output_format()
2923 		drm_WARN_ON(&dev_priv->drm,  in bdw_get_pipe_misc_output_format()
2937 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pipe_config()
2943 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
2948 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
2949 	pipe_config->sink_format = pipe_config->output_format;  in i9xx_get_pipe_config()
2950 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in i9xx_get_pipe_config()
2951 	pipe_config->shared_dpll = NULL;  in i9xx_get_pipe_config()
2955 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));  in i9xx_get_pipe_config()
2963 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
2966 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
2969 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
2979 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
2981 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);  in i9xx_get_pipe_config()
2983 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in i9xx_get_pipe_config()
2987 		pipe_config->wgc_enable = true;  in i9xx_get_pipe_config()
2992 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
3001 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)  in i9xx_get_pipe_config()
3002 			tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];  in i9xx_get_pipe_config()
3004 			tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));  in i9xx_get_pipe_config()
3005 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3007 			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;  in i9xx_get_pipe_config()
3008 		pipe_config->dpll_hw_state.dpll_md = tmp;  in i9xx_get_pipe_config()
3011 		tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));  in i9xx_get_pipe_config()
3012 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3014 			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;  in i9xx_get_pipe_config()
3017 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
3019 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
3021 	pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
3022 							DPLL(crtc->pipe));  in i9xx_get_pipe_config()
3024 		pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
3025 							       FP0(crtc->pipe));  in i9xx_get_pipe_config()
3026 		pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,  in i9xx_get_pipe_config()
3027 							       FP1(crtc->pipe));  in i9xx_get_pipe_config()
3029 		/* Mask out read-only status bits. */  in i9xx_get_pipe_config()
3030 		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |  in i9xx_get_pipe_config()
3047 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
3048 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
3060 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_set_pipeconf()
3061 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_set_pipeconf()
3062 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_set_pipeconf()
3066 	 * - During modeset the pipe is still disabled and must remain so  in ilk_set_pipeconf()
3067 	 * - During fastset the pipe is already enabled and must remain so  in ilk_set_pipeconf()
3072 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3075 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3091 	if (crtc_state->dither)  in ilk_set_pipeconf()
3094 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
3103 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3104 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
3106 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3110 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
3113 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
3115 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in ilk_set_pipeconf()
3116 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);  in ilk_set_pipeconf()
3124 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_transconf()
3125 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_transconf()
3126 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_transconf()
3130 	 * - During modeset the pipe is still disabled and must remain so  in hsw_set_transconf()
3131 	 * - During fastset the pipe is already enabled and must remain so  in hsw_set_transconf()
3136 	if (IS_HASWELL(dev_priv) && crtc_state->dither)  in hsw_set_transconf()
3139 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_transconf()
3145 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_transconf()
3154 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipe_misc()
3155 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_set_pipe_misc()
3158 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3174 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3178 	if (crtc_state->dither)  in bdw_set_pipe_misc()
3181 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipe_misc()
3182 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipe_misc()
3185 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipe_misc()
3199 	intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);  in bdw_set_pipe_misc()
3204 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_bpp()
3207 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_bpp()
3224 	 * MIPI DSI HW readout.  in bdw_get_pipe_misc_bpp()
3252 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3253 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3254 	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3255 	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3256 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;  in intel_get_m_n()
3263 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m1_n1()
3264 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m1_n1()
3280 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m2_n2()
3292 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_get_pfit_config()
3293 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_get_pfit_config()
3297 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));  in ilk_get_pfit_config()
3304 		pipe = crtc->pipe;  in ilk_get_pfit_config()
3306 	crtc_state->pch_pfit.enabled = true;  in ilk_get_pfit_config()
3308 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));  in ilk_get_pfit_config()
3309 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));  in ilk_get_pfit_config()
3311 	drm_rect_init(&crtc_state->pch_pfit.dst,  in ilk_get_pfit_config()
3322 	drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);  in ilk_get_pfit_config()
3328 	struct drm_device *dev = crtc->base.dev;  in ilk_get_pipe_config()
3335 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
3340 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in ilk_get_pipe_config()
3341 	pipe_config->shared_dpll = NULL;  in ilk_get_pipe_config()
3344 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));  in ilk_get_pipe_config()
3350 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3353 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3356 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3359 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3366 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
3371 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
3374 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
3378 	pipe_config->sink_format = pipe_config->output_format;  in ilk_get_pipe_config()
3380 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);  in ilk_get_pipe_config()
3382 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in ilk_get_pipe_config()
3384 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);  in ilk_get_pipe_config()
3388 	pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
3416 	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;  in bigjoiner_pipes()
3442 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,  in enabled_bigjoiner_pipes()
3445 		enum pipe pipe = crtc->pipe;  in enabled_bigjoiner_pipes()
3476 	drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,  in enabled_bigjoiner_pipes()
3490 	return fls(master_pipes) - 1;  in get_bigjoiner_master_pipe()
3507 	next_master_pipe = ffs(master_pipes) - 1;  in get_bigjoiner_slave_pipes()
3509 	return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);  in get_bigjoiner_slave_pipes()
3524 	struct drm_device *dev = crtc->base.dev;  in hsw_enabled_transcoders()
3551 			drm_WARN(dev, 1,  in hsw_enabled_transcoders()
3570 		if (trans_pipe == crtc->pipe)  in hsw_enabled_transcoders()
3575 	cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_enabled_transcoders()
3579 	/* bigjoiner slave -> consider the master pipe's transcoder as well */  in hsw_enabled_transcoders()
3581 	if (slave_pipes & BIT(crtc->pipe)) {  in hsw_enabled_transcoders()
3583 			get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);  in hsw_enabled_transcoders()
3613 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
3616 		    has_pipe_transcoders(enabled_transcoders) > 1);  in assert_enabled_transcoders()
3619 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
3628 	struct drm_device *dev = crtc->base.dev;  in hsw_get_transcoder_state()
3644 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;  in hsw_get_transcoder_state()
3647 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
3650 	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {  in hsw_get_transcoder_state()
3651 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3654 			pipe_config->pch_pfit.force_thru = true;  in hsw_get_transcoder_state()
3657 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3666 	struct drm_device *dev = crtc->base.dev;  in bxt_get_dsi_transcoder_state()
3686 		 * registers/MIPI[BXT]. We can break out here early, since we  in bxt_get_dsi_transcoder_state()
3698 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
3701 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
3705 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
3710 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_bigjoiner_get_config()
3711 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_bigjoiner_get_config()
3713 	enum pipe pipe = crtc->pipe;  in intel_bigjoiner_get_config()
3720 	crtc_state->bigjoiner_pipes =  in intel_bigjoiner_get_config()
3728 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_get_pipe_config()
3732 	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3733 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
3736 	pipe_config->shared_dpll = NULL;  in hsw_get_pipe_config()
3738 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3741 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {  in hsw_get_pipe_config()
3742 		drm_WARN_ON(&dev_priv->drm, active);  in hsw_get_pipe_config()
3752 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
3756 	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))  in hsw_get_pipe_config()
3763 					TRANSCONF(pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3766 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
3768 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
3770 		pipe_config->output_format =  in hsw_get_pipe_config()
3774 	pipe_config->sink_format = pipe_config->output_format;  in hsw_get_pipe_config()
3778 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
3779 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
3781 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
3784 	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3785 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
3794 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
3795 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3796 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
3798 				      TRANS_MULT(pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
3800 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
3803 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3804 		tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3806 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;  in hsw_get_pipe_config()
3809 		pipe_config->framestart_delay = 1;  in hsw_get_pipe_config()
3813 	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3820 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
3821 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_get_pipe_config()
3823 	if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
3826 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
3837 	 * The calculation for the data clock -> pixel clock is:  in intel_dotclock_calculate()
3842 	 * and for link freq (10kbs units) -> pixel clock it is:  in intel_dotclock_calculate()
3849 	if (!m_n->link_n)  in intel_dotclock_calculate()
3852 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),  in intel_dotclock_calculate()
3853 				m_n->link_n * intel_dp_link_symbol_size(link_freq));  in intel_dotclock_calculate()
3861 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_crtc_dotclock()
3862 						    &pipe_config->dp_m_n);  in intel_crtc_dotclock()
3863 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
3864 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,  in intel_crtc_dotclock()
3865 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
3867 		dotclock = pipe_config->port_clock;  in intel_crtc_dotclock()
3869 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&  in intel_crtc_dotclock()
3873 	if (pipe_config->pixel_multiplier)  in intel_crtc_dotclock()
3874 		dotclock /= pipe_config->pixel_multiplier;  in intel_crtc_dotclock()
3883 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_encoder_current_mode()
3889 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
3905 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
3912 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
3914 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
3923 	return a == b || (a->cloneable & BIT(b->type) &&  in encoders_cloneable()
3924 			  b->cloneable & BIT(a->type));  in encoders_cloneable()
3936 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
3937 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
3941 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
3956 		linked = plane_state->planar_linked_plane;  in icl_add_linked_planes()
3965 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
3966 			    linked_plane_state->planar_linked_plane != plane);  in icl_add_linked_planes()
3967 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
3968 			    linked_plane_state->planar_slave == plane_state->planar_slave);  in icl_add_linked_planes()
3976 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_check_nv12_planes()
3977 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_check_nv12_planes()
3978 	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);  in icl_check_nv12_planes()
3988 	 * in the crtc_state->active_planes mask.  in icl_check_nv12_planes()
3991 		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)  in icl_check_nv12_planes()
3994 		plane_state->planar_linked_plane = NULL;  in icl_check_nv12_planes()
3995 		if (plane_state->planar_slave && !plane_state->uapi.visible) {  in icl_check_nv12_planes()
3996 			crtc_state->enabled_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
3997 			crtc_state->active_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
3998 			crtc_state->update_planes |= BIT(plane->id);  in icl_check_nv12_planes()
3999 			crtc_state->data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4000 			crtc_state->rel_data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4003 		plane_state->planar_slave = false;  in icl_check_nv12_planes()
4006 	if (!crtc_state->nv12_planes)  in icl_check_nv12_planes()
4012 		if (plane->pipe != crtc->pipe ||  in icl_check_nv12_planes()
4013 		    !(crtc_state->nv12_planes & BIT(plane->id)))  in icl_check_nv12_planes()
4016 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {  in icl_check_nv12_planes()
4017 			if (!icl_is_nv12_y_plane(dev_priv, linked->id))  in icl_check_nv12_planes()
4020 			if (crtc_state->active_planes & BIT(linked->id))  in icl_check_nv12_planes()
4031 			drm_dbg_kms(&dev_priv->drm,  in icl_check_nv12_planes()
4033 				    hweight8(crtc_state->nv12_planes));  in icl_check_nv12_planes()
4035 			return -EINVAL;  in icl_check_nv12_planes()
4038 		plane_state->planar_linked_plane = linked;  in icl_check_nv12_planes()
4040 		linked_state->planar_slave = true;  in icl_check_nv12_planes()
4041 		linked_state->planar_linked_plane = plane;  in icl_check_nv12_planes()
4042 		crtc_state->enabled_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4043 		crtc_state->active_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4044 		crtc_state->update_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4045 		crtc_state->data_rate[linked->id] =  in icl_check_nv12_planes()
4046 			crtc_state->data_rate_y[plane->id];  in icl_check_nv12_planes()
4047 		crtc_state->rel_data_rate[linked->id] =  in icl_check_nv12_planes()
4048 			crtc_state->rel_data_rate_y[plane->id];  in icl_check_nv12_planes()
4049 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",  in icl_check_nv12_planes()
4050 			    linked->base.name, plane->base.name);  in icl_check_nv12_planes()
4053 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;  in icl_check_nv12_planes()
4054 		linked_state->color_ctl = plane_state->color_ctl;  in icl_check_nv12_planes()
4055 		linked_state->view = plane_state->view;  in icl_check_nv12_planes()
4056 		linked_state->decrypt = plane_state->decrypt;  in icl_check_nv12_planes()
4059 		linked_state->uapi.src = plane_state->uapi.src;  in icl_check_nv12_planes()
4060 		linked_state->uapi.dst = plane_state->uapi.dst;  in icl_check_nv12_planes()
4062 		if (icl_is_hdr_plane(dev_priv, plane->id)) {  in icl_check_nv12_planes()
4063 			if (linked->id == PLANE_SPRITE5)  in icl_check_nv12_planes()
4064 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;  in icl_check_nv12_planes()
4065 			else if (linked->id == PLANE_SPRITE4)  in icl_check_nv12_planes()
4066 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;  in icl_check_nv12_planes()
4067 			else if (linked->id == PLANE_SPRITE3)  in icl_check_nv12_planes()
4068 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;  in icl_check_nv12_planes()
4069 			else if (linked->id == PLANE_SPRITE2)  in icl_check_nv12_planes()
4070 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;  in icl_check_nv12_planes()
4072 				MISSING_CASE(linked->id);  in icl_check_nv12_planes()
4081 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in c8_planes_changed()
4083 		to_intel_atomic_state(new_crtc_state->uapi.state);  in c8_planes_changed()
4087 	return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;  in c8_planes_changed()
4093 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
4096 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
4099 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
4100 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
4109 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
4112 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
4115 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
4116 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
4123 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_linetime_wm()
4124 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_linetime_wm()
4126 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
4129 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
4132 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
4133 				   crtc_state->pixel_rate);  in skl_linetime_wm()
4146 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_compute_linetime_wm()
4152 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4154 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4163 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
4172 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_atomic_check()
4179 	    !crtc_state->hw.active)  in intel_crtc_atomic_check()
4180 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
4193 		crtc_state->uapi.color_mgmt_changed = true;  in intel_crtc_atomic_check()
4203 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
4215 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
4258 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
4259 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in compute_sink_pipe_bpp()
4260 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
4263 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
4277 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
4278 		return -EINVAL;  in compute_sink_pipe_bpp()
4281 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4282 		drm_dbg_kms(&i915->drm,  in compute_sink_pipe_bpp()
4285 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
4286 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
4287 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
4288 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4290 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4300 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in compute_baseline_pipe_bpp()
4315 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
4318 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in compute_baseline_pipe_bpp()
4321 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
4334 	struct drm_device *dev = state->base.dev;  in check_digital_port_conflicts()
4342 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
4345 	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);  in check_digital_port_conflicts()
4358 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
4361 			connector_state = connector->state;  in check_digital_port_conflicts()
4363 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
4366 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
4368 		drm_WARN_ON(dev, !connector_state->crtc);  in check_digital_port_conflicts()
4370 		switch (encoder->type) {  in check_digital_port_conflicts()
4379 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
4382 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
4386 				1 << encoder->port;  in check_digital_port_conflicts()
4410 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4411 				  crtc_state->uapi.degamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4412 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4413 				  crtc_state->uapi.gamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4414 	drm_property_replace_blob(&crtc_state->hw.ctm,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4415 				  crtc_state->uapi.ctm);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4427 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4428 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4429 	drm_mode_copy(&crtc_state->hw.mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4430 		      &crtc_state->uapi.mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4431 	drm_mode_copy(&crtc_state->hw.adjusted_mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4432 		      &crtc_state->uapi.adjusted_mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4433 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4448 	drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,  in copy_bigjoiner_crtc_state_nomodeset()
4449 				  master_crtc_state->hw.degamma_lut);  in copy_bigjoiner_crtc_state_nomodeset()
4450 	drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,  in copy_bigjoiner_crtc_state_nomodeset()
4451 				  master_crtc_state->hw.gamma_lut);  in copy_bigjoiner_crtc_state_nomodeset()
4452 	drm_property_replace_blob(&slave_crtc_state->hw.ctm,  in copy_bigjoiner_crtc_state_nomodeset()
4453 				  master_crtc_state->hw.ctm);  in copy_bigjoiner_crtc_state_nomodeset()
4455 	slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;  in copy_bigjoiner_crtc_state_nomodeset()
4469 	WARN_ON(master_crtc_state->bigjoiner_pipes !=  in copy_bigjoiner_crtc_state_modeset()
4470 		slave_crtc_state->bigjoiner_pipes);  in copy_bigjoiner_crtc_state_modeset()
4474 		return -ENOMEM;  in copy_bigjoiner_crtc_state_modeset()
4477 	saved_state->uapi = slave_crtc_state->uapi;  in copy_bigjoiner_crtc_state_modeset()
4478 	saved_state->scaler_state = slave_crtc_state->scaler_state;  in copy_bigjoiner_crtc_state_modeset()
4479 	saved_state->shared_dpll = slave_crtc_state->shared_dpll;  in copy_bigjoiner_crtc_state_modeset()
4480 	saved_state->crc_enabled = slave_crtc_state->crc_enabled;  in copy_bigjoiner_crtc_state_modeset()
4486 	/* Re-init hw state */  in copy_bigjoiner_crtc_state_modeset()
4487 	memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));  in copy_bigjoiner_crtc_state_modeset()
4488 	slave_crtc_state->hw.enable = master_crtc_state->hw.enable;  in copy_bigjoiner_crtc_state_modeset()
4489 	slave_crtc_state->hw.active = master_crtc_state->hw.active;  in copy_bigjoiner_crtc_state_modeset()
4490 	drm_mode_copy(&slave_crtc_state->hw.mode,  in copy_bigjoiner_crtc_state_modeset()
4491 		      &master_crtc_state->hw.mode);  in copy_bigjoiner_crtc_state_modeset()
4492 	drm_mode_copy(&slave_crtc_state->hw.pipe_mode,  in copy_bigjoiner_crtc_state_modeset()
4493 		      &master_crtc_state->hw.pipe_mode);  in copy_bigjoiner_crtc_state_modeset()
4494 	drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,  in copy_bigjoiner_crtc_state_modeset()
4495 		      &master_crtc_state->hw.adjusted_mode);  in copy_bigjoiner_crtc_state_modeset()
4496 	slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;  in copy_bigjoiner_crtc_state_modeset()
4500 	slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;  in copy_bigjoiner_crtc_state_modeset()
4501 	slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;  in copy_bigjoiner_crtc_state_modeset()
4502 	slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;  in copy_bigjoiner_crtc_state_modeset()
4504 	WARN_ON(master_crtc_state->bigjoiner_pipes !=  in copy_bigjoiner_crtc_state_modeset()
4505 		slave_crtc_state->bigjoiner_pipes);  in copy_bigjoiner_crtc_state_modeset()
4516 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_prepare_cleared_state()
4521 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
4523 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
4531 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
4532 	saved_state->inherited = crtc_state->inherited;  in intel_crtc_prepare_cleared_state()
4533 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
4534 	saved_state->shared_dpll = crtc_state->shared_dpll;  in intel_crtc_prepare_cleared_state()
4535 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
4536 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
4537 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
4538 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
4541 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
4556 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_modeset_pipe_config()
4564 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;  in intel_modeset_pipe_config()
4566 	crtc_state->framestart_delay = 1;  in intel_modeset_pipe_config()
4573 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4575 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
4577 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4579 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
4585 	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);  in intel_modeset_pipe_config()
4586 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];  in intel_modeset_pipe_config()
4588 	if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {  in intel_modeset_pipe_config()
4589 		drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4591 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4592 			    BPP_X16_ARGS(crtc_state->max_link_bpp_x16));  in intel_modeset_pipe_config()
4593 		crtc_state->bw_constrained = true;  in intel_modeset_pipe_config()
4596 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4606 	drm_mode_get_hv_timing(&crtc_state->hw.mode,  in intel_modeset_pipe_config()
4608 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_modeset_pipe_config()
4611 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4613 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4615 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4619 			drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4621 				    encoder->base.base.id, encoder->base.name);  in intel_modeset_pipe_config()
4622 			return -EINVAL;  in intel_modeset_pipe_config()
4629 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
4630 			crtc_state->output_types |=  in intel_modeset_pipe_config()
4631 				BIT(encoder->compute_output_type(encoder, crtc_state,  in intel_modeset_pipe_config()
4634 			crtc_state->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
4638 	crtc_state->port_clock = 0;  in intel_modeset_pipe_config()
4639 	crtc_state->pixel_multiplier = 1;  in intel_modeset_pipe_config()
4642 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,  in intel_modeset_pipe_config()
4649 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4651 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4653 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4656 		ret = encoder->compute_config(encoder, crtc_state,  in intel_modeset_pipe_config()
4658 		if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4661 			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4662 				    encoder->base.base.id, encoder->base.name, ret);  in intel_modeset_pipe_config()
4669 	if (!crtc_state->port_clock)  in intel_modeset_pipe_config()
4670 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
4671 			* crtc_state->pixel_multiplier;  in intel_modeset_pipe_config()
4674 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4677 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4678 			    crtc->base.base.id, crtc->base.name, ret);  in intel_modeset_pipe_config()
4682 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
4686 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
4687 		!crtc_state->dither_force_disable;  in intel_modeset_pipe_config()
4688 	drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4690 		    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4691 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
4708 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
4711 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
4714 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
4715 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
4718 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
4737 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
4749 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
4750 		m_n->data_m == m2_n2->data_m &&  in intel_compare_link_m_n()
4751 		m_n->data_n == m2_n2->data_n &&  in intel_compare_link_m_n()
4752 		m_n->link_m == m2_n2->link_m &&  in intel_compare_link_m_n()
4753 		m_n->link_n == m2_n2->link_n;  in intel_compare_link_m_n()
4786 		drm_dbg_kms(&dev_priv->drm,  in pipe_config_infoframe_mismatch()
4788 		drm_dbg_kms(&dev_priv->drm, "expected:\n");  in pipe_config_infoframe_mismatch()
4789 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);  in pipe_config_infoframe_mismatch()
4790 		drm_dbg_kms(&dev_priv->drm, "found:\n");  in pipe_config_infoframe_mismatch()
4791 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);  in pipe_config_infoframe_mismatch()
4793 		drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);  in pipe_config_infoframe_mismatch()
4794 		drm_err(&dev_priv->drm, "expected:\n");  in pipe_config_infoframe_mismatch()
4795 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);  in pipe_config_infoframe_mismatch()
4796 		drm_err(&dev_priv->drm, "found:\n");  in pipe_config_infoframe_mismatch()
4797 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);  in pipe_config_infoframe_mismatch()
4811 		drm_dbg_kms(&dev_priv->drm,  in pipe_config_dp_vsc_sdp_mismatch()
4813 		drm_dbg_kms(&dev_priv->drm, "expected:\n");  in pipe_config_dp_vsc_sdp_mismatch()
4814 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);  in pipe_config_dp_vsc_sdp_mismatch()
4815 		drm_dbg_kms(&dev_priv->drm, "found:\n");  in pipe_config_dp_vsc_sdp_mismatch()
4816 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);  in pipe_config_dp_vsc_sdp_mismatch()
4818 		drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);  in pipe_config_dp_vsc_sdp_mismatch()
4819 		drm_err(&dev_priv->drm, "expected:\n");  in pipe_config_dp_vsc_sdp_mismatch()
4820 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);  in pipe_config_dp_vsc_sdp_mismatch()
4821 		drm_err(&dev_priv->drm, "found:\n");  in pipe_config_dp_vsc_sdp_mismatch()
4822 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);  in pipe_config_dp_vsc_sdp_mismatch()
4832 	for (i = len - 1; i >= 0; i--) {  in memcmp_diff_len()
4834 			return i + 1;  in memcmp_diff_len()
4852 		drm_dbg_kms(&dev_priv->drm,  in pipe_config_buffer_mismatch()
4862 		drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);  in pipe_config_buffer_mismatch()
4874 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_mismatch()
4883 		drm_dbg_kms(&i915->drm,  in pipe_config_mismatch()
4885 			    crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4887 		drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",  in pipe_config_mismatch()
4888 			crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4912 	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);  in intel_pipe_config_compare()
4913 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
4916 		current_config->inherited && !pipe_config->inherited;  in intel_pipe_config_compare()
4919 		drm_dbg_kms(&dev_priv->drm,  in intel_pipe_config_compare()
4925 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
4926 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4930 				     current_config->name, \  in intel_pipe_config_compare()
4931 				     pipe_config->name); \  in intel_pipe_config_compare()
4937 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
4938 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4942 				     current_config->name & (mask), \  in intel_pipe_config_compare()
4943 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
4949 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
4950 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4954 				     current_config->name, \  in intel_pipe_config_compare()
4955 				     pipe_config->name); \  in intel_pipe_config_compare()
4961 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
4962 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4966 				     str_yes_no(current_config->name), \  in intel_pipe_config_compare()
4967 				     str_yes_no(pipe_config->name)); \  in intel_pipe_config_compare()
4973 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
4976 				     current_config->name, \  in intel_pipe_config_compare()
4977 				     pipe_config->name); \  in intel_pipe_config_compare()
4983 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
4984 				    &pipe_config->name)) { \  in intel_pipe_config_compare()
4988 				     current_config->name.tu, \  in intel_pipe_config_compare()
4989 				     current_config->name.data_m, \  in intel_pipe_config_compare()
4990 				     current_config->name.data_n, \  in intel_pipe_config_compare()
4991 				     current_config->name.link_m, \  in intel_pipe_config_compare()
4992 				     current_config->name.link_n, \  in intel_pipe_config_compare()
4993 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
4994 				     pipe_config->name.data_m, \  in intel_pipe_config_compare()
4995 				     pipe_config->name.data_n, \  in intel_pipe_config_compare()
4996 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
4997 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
5013 	if (!fastset || !pipe_config->update_lrr) { \  in intel_pipe_config_compare()
5027 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
5031 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5032 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5038 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5039 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5041 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
5042 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5048 	if (!current_config->has_psr && !pipe_config->has_psr && \  in intel_pipe_config_compare()
5049 	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5050 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5052 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5053 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5059 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \  in intel_pipe_config_compare()
5060 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \  in intel_pipe_config_compare()
5061 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \  in intel_pipe_config_compare()
5063 					    current_config->name, \  in intel_pipe_config_compare()
5064 					    pipe_config->name, \  in intel_pipe_config_compare()
5071 	if (current_config->gamma_mode == pipe_config->gamma_mode && \  in intel_pipe_config_compare()
5073 				   current_config->lut, pipe_config->lut, \  in intel_pipe_config_compare()
5083 	PIPE_CONF_CHECK_X(name.preoff[1]); \  in intel_pipe_config_compare()
5086 	PIPE_CONF_CHECK_X(name.coeff[1]); \  in intel_pipe_config_compare()
5095 	PIPE_CONF_CHECK_X(name.postoff[1]); \  in intel_pipe_config_compare()
5100 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
5116 		if (!fastset || !pipe_config->update_m_n)  in intel_pipe_config_compare()
5203 		if (current_config->active_planes) {  in intel_pipe_config_compare()
5213 	if (dev_priv->display.dpll.mgr) {  in intel_pipe_config_compare()
5256 	if (!fastset || !pipe_config->update_m_n) {  in intel_pipe_config_compare()
5264 	if (current_config->has_psr || pipe_config->has_psr)  in intel_pipe_config_compare()
5351 		assert_plane(plane, plane_state->planar_slave ||  in intel_verify_planes()
5352 			     plane_state->uapi.visible);  in intel_verify_planes()
5359 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipe()
5360 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe()
5363 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",  in intel_modeset_pipe()
5364 		    crtc->base.base.id, crtc->base.name, reason);  in intel_modeset_pipe()
5366 	ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_pipe()
5367 						 &crtc->base);  in intel_modeset_pipe()
5379 	crtc_state->uapi.mode_changed = true;  in intel_modeset_pipe()
5385  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5399 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipes_in_mask_early()
5402 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {  in intel_modeset_pipes_in_mask_early()
5406 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_pipes_in_mask_early()
5410 		if (!crtc_state->hw.enable ||  in intel_modeset_pipes_in_mask_early()
5425 	crtc_state->uapi.mode_changed = true;  in intel_crtc_flag_modeset()
5427 	crtc_state->update_pipe = false;  in intel_crtc_flag_modeset()
5428 	crtc_state->update_m_n = false;  in intel_crtc_flag_modeset()
5429 	crtc_state->update_lrr = false;  in intel_crtc_flag_modeset()
5433  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5446 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_all_pipes_late()
5449 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_all_pipes_late()
5453 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes_late()
5457 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes_late()
5467 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes_late()
5468 		crtc_state->async_flip_planes = 0;  in intel_modeset_all_pipes_late()
5469 		crtc_state->do_async_flip = false;  in intel_modeset_all_pipes_late()
5492 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5501 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5510 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
5511 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
5515 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
5517 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5525 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5529 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
5531 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
5544 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
5545 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
5547 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
5555 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_checks()
5557 	state->modeset = true;  in intel_modeset_checks()
5568 	struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);  in intel_crtc_check_fastset()
5571 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)  in intel_crtc_check_fastset()
5572 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5575 		drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");  in intel_crtc_check_fastset()
5577 		new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
5579 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,  in intel_crtc_check_fastset()
5580 				   &new_crtc_state->dp_m_n))  in intel_crtc_check_fastset()
5581 		new_crtc_state->update_m_n = false;  in intel_crtc_check_fastset()
5583 …if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal …  in intel_crtc_check_fastset()
5584 …old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_e…  in intel_crtc_check_fastset()
5585 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5590 		new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
5597 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_crtc_add_planes_to_state()
5600 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_crtc_add_planes_to_state()
5603 		if ((plane_ids_mask & BIT(plane->id)) == 0)  in intel_crtc_add_planes_to_state()
5623 					      old_crtc_state->enabled_planes |  in intel_atomic_add_affected_planes()
5624 					      new_crtc_state->enabled_planes);  in intel_atomic_add_affected_planes()
5645 		if (plane->pipe == crtc->pipe)  in intel_crtc_add_bigjoiner_planes()
5646 			plane_ids |= BIT(plane->id);  in intel_crtc_add_bigjoiner_planes()
5654 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_bigjoiner_add_affected_planes()
5662 		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,  in intel_bigjoiner_add_affected_planes()
5663 						 crtc_state->bigjoiner_pipes) {  in intel_bigjoiner_add_affected_planes()
5680 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_check_planes()
5698 			drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_check_planes()
5700 				       plane->base.base.id, plane->base.name);  in intel_atomic_check_planes()
5721 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
5722 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
5742 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_atomic_check_crtcs()
5747 			drm_dbg_atomic(&i915->drm,  in intel_atomic_check_crtcs()
5749 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
5765 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
5766 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
5782 		if (new_crtc_state->hw.enable &&  in intel_pipes_need_modeset()
5783 		    pipes & BIT(crtc->pipe) &&  in intel_pipes_need_modeset()
5794 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_bigjoiner()
5799 	if (!master_crtc_state->bigjoiner_pipes)  in intel_atomic_check_bigjoiner()
5803 	if (drm_WARN_ON(&i915->drm,  in intel_atomic_check_bigjoiner()
5804 			master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))  in intel_atomic_check_bigjoiner()
5805 		return -EINVAL;  in intel_atomic_check_bigjoiner()
5807 	if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {  in intel_atomic_check_bigjoiner()
5808 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_bigjoiner()
5811 			    master_crtc->base.base.id, master_crtc->base.name,  in intel_atomic_check_bigjoiner()
5812 			    master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));  in intel_atomic_check_bigjoiner()
5813 		return -EINVAL;  in intel_atomic_check_bigjoiner()
5816 	for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,  in intel_atomic_check_bigjoiner()
5821 		slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);  in intel_atomic_check_bigjoiner()
5826 		if (slave_crtc_state->uapi.enable) {  in intel_atomic_check_bigjoiner()
5827 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_bigjoiner()
5830 				    slave_crtc->base.base.id, slave_crtc->base.name,  in intel_atomic_check_bigjoiner()
5831 				    master_crtc->base.base.id, master_crtc->base.name);  in intel_atomic_check_bigjoiner()
5832 			return -EINVAL;  in intel_atomic_check_bigjoiner()
5842 		if (WARN_ON(drm_crtc_index(&master_crtc->base) >  in intel_atomic_check_bigjoiner()
5843 			    drm_crtc_index(&slave_crtc->base)))  in intel_atomic_check_bigjoiner()
5844 			return -EINVAL;  in intel_atomic_check_bigjoiner()
5846 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_bigjoiner()
5848 			    slave_crtc->base.base.id, slave_crtc->base.name,  in intel_atomic_check_bigjoiner()
5849 			    master_crtc->base.base.id, master_crtc->base.name);  in intel_atomic_check_bigjoiner()
5851 		slave_crtc_state->bigjoiner_pipes =  in intel_atomic_check_bigjoiner()
5852 			master_crtc_state->bigjoiner_pipes;  in intel_atomic_check_bigjoiner()
5865 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in kill_bigjoiner_slave()
5870 	for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,  in kill_bigjoiner_slave()
5875 		slave_crtc_state->bigjoiner_pipes = 0;  in kill_bigjoiner_slave()
5880 	master_crtc_state->bigjoiner_pipes = 0;  in kill_bigjoiner_slave()
5904 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_uapi()
5912 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_uapi()
5915 	if (!new_crtc_state->uapi.active) {  in intel_async_flip_check_uapi()
5916 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
5918 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5919 		return -EINVAL;  in intel_async_flip_check_uapi()
5923 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
5925 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5926 		return -EINVAL;  in intel_async_flip_check_uapi()
5933 	if (new_crtc_state->bigjoiner_pipes) {  in intel_async_flip_check_uapi()
5934 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
5936 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5937 		return -EINVAL;  in intel_async_flip_check_uapi()
5942 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_uapi()
5952 		if (!plane->async_flip) {  in intel_async_flip_check_uapi()
5953 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
5955 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
5956 			return -EINVAL;  in intel_async_flip_check_uapi()
5959 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {  in intel_async_flip_check_uapi()
5960 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
5962 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
5963 			return -EINVAL;  in intel_async_flip_check_uapi()
5972 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_hw()
5981 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_hw()
5984 	if (!new_crtc_state->hw.active) {  in intel_async_flip_check_hw()
5985 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
5987 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
5988 		return -EINVAL;  in intel_async_flip_check_hw()
5992 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
5994 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
5995 		return -EINVAL;  in intel_async_flip_check_hw()
5998 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_async_flip_check_hw()
5999 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6001 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6002 		return -EINVAL;  in intel_async_flip_check_hw()
6007 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_hw()
6015 		if (drm_WARN_ON(&i915->drm,  in intel_async_flip_check_hw()
6016 				new_crtc_state->do_async_flip && !plane->async_flip))  in intel_async_flip_check_hw()
6017 			return -EINVAL;  in intel_async_flip_check_hw()
6027 		if (!plane->async_flip)  in intel_async_flip_check_hw()
6035 		switch (new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6044 				drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6046 					    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6047 					    new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));  in intel_async_flip_check_hw()
6048 				return -EINVAL;  in intel_async_flip_check_hw()
6058 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6060 				    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6061 				    new_plane_state->hw.fb->modifier);  in intel_async_flip_check_hw()
6062 			return -EINVAL;  in intel_async_flip_check_hw()
6065 		if (new_plane_state->hw.fb->format->num_planes > 1) {  in intel_async_flip_check_hw()
6066 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6068 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6069 			return -EINVAL;  in intel_async_flip_check_hw()
6072 		if (old_plane_state->view.color_plane[0].mapping_stride !=  in intel_async_flip_check_hw()
6073 		    new_plane_state->view.color_plane[0].mapping_stride) {  in intel_async_flip_check_hw()
6074 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6076 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6077 			return -EINVAL;  in intel_async_flip_check_hw()
6080 		if (old_plane_state->hw.fb->modifier !=  in intel_async_flip_check_hw()
6081 		    new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6082 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6084 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6085 			return -EINVAL;  in intel_async_flip_check_hw()
6088 		if (old_plane_state->hw.fb->format !=  in intel_async_flip_check_hw()
6089 		    new_plane_state->hw.fb->format) {  in intel_async_flip_check_hw()
6090 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6092 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6093 			return -EINVAL;  in intel_async_flip_check_hw()
6096 		if (old_plane_state->hw.rotation !=  in intel_async_flip_check_hw()
6097 		    new_plane_state->hw.rotation) {  in intel_async_flip_check_hw()
6098 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6100 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6101 			return -EINVAL;  in intel_async_flip_check_hw()
6104 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_async_flip_check_hw()
6105 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_async_flip_check_hw()
6106 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6107 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6108 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6109 			return -EINVAL;  in intel_async_flip_check_hw()
6112 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_async_flip_check_hw()
6113 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6115 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6116 			return -EINVAL;  in intel_async_flip_check_hw()
6119 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_async_flip_check_hw()
6120 		    new_plane_state->hw.pixel_blend_mode) {  in intel_async_flip_check_hw()
6121 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6123 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6124 			return -EINVAL;  in intel_async_flip_check_hw()
6127 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_async_flip_check_hw()
6128 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6130 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6131 			return -EINVAL;  in intel_async_flip_check_hw()
6134 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_async_flip_check_hw()
6135 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6137 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6138 			return -EINVAL;  in intel_async_flip_check_hw()
6142 		if (old_plane_state->decrypt != new_plane_state->decrypt) {  in intel_async_flip_check_hw()
6143 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6145 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6146 			return -EINVAL;  in intel_async_flip_check_hw()
6155 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_bigjoiner_add_affected_crtcs()
6163 		affected_pipes |= crtc_state->bigjoiner_pipes;  in intel_bigjoiner_add_affected_crtcs()
6165 			modeset_pipes |= crtc_state->bigjoiner_pipes;  in intel_bigjoiner_add_affected_crtcs()
6168 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {  in intel_bigjoiner_add_affected_crtcs()
6169 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_bigjoiner_add_affected_crtcs()
6174 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {  in intel_bigjoiner_add_affected_crtcs()
6179 		crtc_state->uapi.mode_changed = true;  in intel_bigjoiner_add_affected_crtcs()
6181 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_bigjoiner_add_affected_crtcs()
6191 		/* Kill old bigjoiner link, we may re-establish afterwards */  in intel_bigjoiner_add_affected_crtcs()
6204 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_config()
6230 			drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);  in intel_atomic_check_config()
6238 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6251 		*failed_pipe = crtc->pipe;  in intel_atomic_check_config()
6258 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_config_and_link()
6276 			if (ret == -EINVAL &&  in intel_atomic_check_config_and_link()
6289 		if (ret != -EAGAIN)  in intel_atomic_check_config_and_link()
6296  * intel_atomic_check - validate state object
6316 		if (!state->internal)  in intel_atomic_check()
6317 			new_crtc_state->inherited = false;  in intel_atomic_check()
6319 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
6320 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6322 		if (new_crtc_state->uapi.scaling_filter !=  in intel_atomic_check()
6323 		    old_crtc_state->uapi.scaling_filter)  in intel_atomic_check()
6324 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6329 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
6348 		if (new_crtc_state->hw.enable) {  in intel_atomic_check()
6369 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
6376 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
6383 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
6385 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
6386 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
6392 		if (new_crtc_state->bigjoiner_pipes) {  in intel_atomic_check()
6393 			if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))  in intel_atomic_check()
6409 		drm_dbg_kms(&dev_priv->drm,  in intel_atomic_check()
6411 		ret = -EINVAL;  in intel_atomic_check()
6465 		drm_WARN_ON(&dev_priv->drm,  in intel_atomic_check()
6481 	if (ret == -EDEADLK)  in intel_atomic_check()
6501 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
6516 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_arm_fifo_underrun()
6518 	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
6519 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
6521 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
6532 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
6533 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pipe_fastset()
6547 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6550 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6552 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6568 	if (new_crtc_state->update_m_n)  in intel_pipe_fastset()
6569 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,  in intel_pipe_fastset()
6570 					       &new_crtc_state->dp_m_n);  in intel_pipe_fastset()
6572 	if (new_crtc_state->update_lrr)  in intel_pipe_fastset()
6579 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_pre_planes()
6609 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_post_planes()
6631 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_enable_crtc()
6641 	dev_priv->display.funcs.display->crtc_enable(state, crtc);  in intel_enable_crtc()
6646 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
6653 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_pre_update_crtc()
6660 	if (old_crtc_state->inherited ||  in intel_pre_update_crtc()
6667 		if (new_crtc_state->preload_luts &&  in intel_pre_update_crtc()
6686 	drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));  in intel_pre_update_crtc()
6720 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)  in intel_update_crtc()
6722 						 new_crtc_state->vrr.enable);  in intel_update_crtc()
6731 	    old_crtc_state->inherited)  in intel_update_crtc()
6740 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_old_crtc_state_disables()
6748 	dev_priv->display.funcs.display->crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
6749 	crtc->active = false;  in intel_old_crtc_state_disables()
6752 	if (!new_crtc_state->hw.active)  in intel_old_crtc_state_disables()
6770 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
6782 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
6797 		handled |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
6804 		    (handled & BIT(crtc->pipe)))  in intel_commit_modeset_disables()
6807 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
6822 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
6830 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
6839 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in skl_commit_modeset_enables()
6847 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6849 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
6854 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
6871 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6882 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6887 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
6891 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
6902 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
6903 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
6916 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6936 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6950 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6959 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6964 		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
6967 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
6973 	drm_WARN_ON(&dev_priv->drm, modeset_pipes);  in skl_commit_modeset_enables()
6974 	drm_WARN_ON(&dev_priv->drm, update_pipes);  in skl_commit_modeset_enables()
6979 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
6984 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {  in intel_atomic_commit_fence_wait()
6985 		if (new_plane_state->fence) {  in intel_atomic_commit_fence_wait()
6986 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,  in intel_atomic_commit_fence_wait()
6991 			dma_fence_put(new_plane_state->fence);  in intel_atomic_commit_fence_wait()
6992 			new_plane_state->fence = NULL;  in intel_atomic_commit_fence_wait()
7001 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_cleanup_work()
7009 	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);  in intel_atomic_cleanup_work()
7010 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
7011 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
7016 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_prepare_plane_clear_colors()
7022 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
7037 		 * plane #1 for flat ccs):  in intel_atomic_prepare_plane_clear_colors()
7038 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
7040 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
7042 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
7049 						     fb->offsets[cc_plane] + 16,  in intel_atomic_prepare_plane_clear_colors()
7050 						     &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
7051 						     sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
7053 		drm_WARN_ON(&i915->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
7059 	struct drm_device *dev = state->base.dev;  in intel_atomic_commit_tail()
7069 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7070 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7079 	 * 1. DC5 exit and PSR exit happen  in intel_atomic_commit_tail()
7081 	 * 3. Due to some long delay PSR is re-entered  in intel_atomic_commit_tail()
7082 	 * 4. DC5 entry -> DMC saves the already written new  in intel_atomic_commit_tail()
7085 	 * 5. DC5 exit -> DMC restores a mixture of old and  in intel_atomic_commit_tail()
7087 	 * 6. PSR exit -> hardware latches a mixture of old and  in intel_atomic_commit_tail()
7088 	 *    new register values -> corrupted frame, or worse  in intel_atomic_commit_tail()
7107 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7112 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
7114 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
7124 	if (state->modeset) {  in intel_atomic_commit_tail()
7125 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);  in intel_atomic_commit_tail()
7139 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
7140 			spin_lock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7141 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
7142 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
7143 			spin_unlock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7145 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
7155 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7160 	dev_priv->display.funcs.display->commit_modeset_enables(state);  in intel_atomic_commit_tail()
7162 	if (state->modeset)  in intel_atomic_commit_tail()
7170 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
7171 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
7172 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
7173 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
7176 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);  in intel_atomic_commit_tail()
7179 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7187 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
7196 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
7203 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_atomic_commit_tail()
7213 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7231 		 * FIXME get rid of this funny new->old swapping  in intel_atomic_commit_tail()
7233 		old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);  in intel_atomic_commit_tail()
7240 	if (state->modeset)  in intel_atomic_commit_tail()
7246 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
7248 	if (state->modeset) {  in intel_atomic_commit_tail()
7252 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
7255 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
7258 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off  in intel_atomic_commit_tail()
7262 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit_tail()
7267 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
7272 	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
7273 	queue_work(system_highpri_wq, &state->base.commit_work);  in intel_atomic_commit_tail()
7292 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
7293 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
7294 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
7304 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_atomic_commit()
7314 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
7323 	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
7329 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
7330 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
7331 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
7336 		drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_commit()
7338 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7342 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_commit()
7344 		ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_commit()
7356 		drm_atomic_helper_unprepare_planes(dev, &state->base);  in intel_atomic_commit()
7357 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7363 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
7364 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
7366 	if (nonblock && state->modeset) {  in intel_atomic_commit()
7367 		queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);  in intel_atomic_commit()
7369 		queue_work(dev_priv->display.wq.flip, &state->base.commit_work);  in intel_atomic_commit()
7371 		if (state->modeset)  in intel_atomic_commit()
7372 			flush_workqueue(dev_priv->display.wq.modeset);  in intel_atomic_commit()
7380  * intel_plane_destroy - destroy a plane
7399 	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);  in intel_get_pipe_from_crtc_id_ioctl()
7401 		return -ENOENT;  in intel_get_pipe_from_crtc_id_ioctl()
7404 	pipe_from_crtc_id->pipe = crtc->pipe;  in intel_get_pipe_from_crtc_id_ioctl()
7411 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_clones()
7417 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
7425 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_crtcs()
7429 	for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)  in intel_encoder_possible_crtcs()
7430 		possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
7465 	if (!dev_priv->display.vbt.int_crt_support)  in intel_ddi_crt_present()
7473 	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),  in assert_port_valid()
7534 		if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)  in intel_setup_outputs()
7540 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
7547 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
7591 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");  in intel_setup_outputs()
7594 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
7606 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");  in intel_setup_outputs()
7613 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
7634 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_setup_outputs()
7635 		encoder->base.possible_crtcs =  in intel_setup_outputs()
7637 		encoder->base.possible_clones =  in intel_setup_outputs()
7643 	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);  in intel_setup_outputs()
7648 	int max_dotclock = i915->max_dotclk_freq;  in max_dotclock()
7672 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
7673 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
7677 	if (mode->vscan > 1)  in intel_mode_valid()
7680 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
7683 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
7688 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
7697 	if (mode->clock > max_dotclock(dev_priv))  in intel_mode_valid()
7724 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
7725 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
7726 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
7727 	    mode->htotal > htotal_max)  in intel_mode_valid()
7730 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
7731 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
7732 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
7733 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
7747 		if (mode->hdisplay < 64 ||  in intel_cpu_transcoder_mode_valid()
7748 		    mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
7751 		if (mode->vtotal - mode->vdisplay < 5)  in intel_cpu_transcoder_mode_valid()
7754 		if (mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
7757 		if (mode->vtotal - mode->vdisplay < 3)  in intel_cpu_transcoder_mode_valid()
7766 	    mode->hsync_start == mode->hdisplay)  in intel_cpu_transcoder_mode_valid()
7799 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
7802 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
7849  * intel_init_display_hooks - initialize the display modesetting hooks
7855 		dev_priv->display.funcs.display = &skl_display_funcs;  in intel_init_display_hooks()
7857 		dev_priv->display.funcs.display = &ddi_display_funcs;  in intel_init_display_hooks()
7859 		dev_priv->display.funcs.display = &pch_split_display_funcs;  in intel_init_display_hooks()
7862 		dev_priv->display.funcs.display = &vlv_display_funcs;  in intel_init_display_hooks()
7864 		dev_priv->display.funcs.display = &i9xx_display_funcs;  in intel_init_display_hooks()
7877 		return -ENOMEM;  in intel_initial_commit()
7881 	state->acquire_ctx = &ctx;  in intel_initial_commit()
7882 	to_intel_atomic_state(state)->internal = true;  in intel_initial_commit()
7894 		if (crtc_state->hw.active) {  in intel_initial_commit()
7897 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
7907 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
7910 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
7911 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
7912 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
7914 										 &crtc->base);  in intel_initial_commit()
7925 	if (ret == -EDEADLK) {  in intel_initial_commit()
7954 	drm_WARN_ON(&dev_priv->drm,  in i830_enable_pipe()
7957 	drm_dbg_kms(&dev_priv->drm,  in i830_enable_pipe()
7964 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
7970 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));  in i830_enable_pipe()
7972 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));  in i830_enable_pipe()
7974 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));  in i830_enable_pipe()
7976 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));  in i830_enable_pipe()
7978 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));  in i830_enable_pipe()
7980 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));  in i830_enable_pipe()
7982 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));  in i830_enable_pipe()
8023 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
8026 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8028 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8030 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8032 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8034 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8052 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_hpd_poll_fini()
8054 		if (connector->modeset_retry_work.func)  in intel_hpd_poll_fini()
8055 			cancel_work_sync(&connector->modeset_retry_work);  in intel_hpd_poll_fini()
8056 		if (connector->hdcp.shim) {  in intel_hpd_poll_fini()
8057 			cancel_delayed_work_sync(&connector->hdcp.check_work);  in intel_hpd_poll_fini()
8058 			cancel_work_sync(&connector->hdcp.prop_work);  in intel_hpd_poll_fini()