Lines Matching +full:port +full:- +full:base
97 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
99 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
115 * Starting with Haswell, DDI port buffers must be programmed with correct
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
125 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
128 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
129 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
134 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
138 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
139 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
140 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), in hsw_prepare_dp_ddi_buffers()
141 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
146 * Starting with Haswell, DDI port buffers must be programmed with correct
153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
157 enum port port = encoder->port; in hsw_prepare_hdmi_ddi_buffers() local
160 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_hdmi_ddi_buffers()
161 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_hdmi_ddi_buffers()
166 intel_bios_hdmi_boost_level(encoder->devdata)) in hsw_prepare_hdmi_ddi_buffers()
170 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), in hsw_prepare_hdmi_ddi_buffers()
171 trans->entries[level].hsw.trans1 | iboost_bit); in hsw_prepare_hdmi_ddi_buffers()
172 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), in hsw_prepare_hdmi_ddi_buffers()
173 trans->entries[level].hsw.trans2); in hsw_prepare_hdmi_ddi_buffers()
176 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) in mtl_wait_ddi_buf_idle() argument
181 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & in mtl_wait_ddi_buf_idle()
184 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", in mtl_wait_ddi_buf_idle()
185 port_name(port)); in mtl_wait_ddi_buf_idle()
189 enum port port) in intel_wait_ddi_buf_idle() argument
196 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
198 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
199 port_name(port)); in intel_wait_ddi_buf_idle()
203 enum port port) in intel_wait_ddi_buf_active() argument
205 enum phy phy = intel_port_to_phy(dev_priv, port); in intel_wait_ddi_buf_active()
229 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE), in intel_wait_ddi_buf_active()
232 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), in intel_wait_ddi_buf_active()
236 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
237 port_name(port)); in intel_wait_ddi_buf_active()
242 switch (pll->info->id) { in hsw_pll_to_ddi_pll_sel()
256 MISSING_CASE(pll->info->id); in hsw_pll_to_ddi_pll_sel()
264 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
265 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
266 const enum intel_dpll_id id = pll->info->id; in icl_pll_to_ddi_clk_sel()
328 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_init_dp_buf_reg()
331 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_init_dp_buf_reg()
334 intel_dp->DP = dig_port->saved_port_bits | in intel_ddi_init_dp_buf_reg()
335 DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
340 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; in intel_ddi_init_dp_buf_reg()
342 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; in intel_ddi_init_dp_buf_reg()
346 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
348 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; in intel_ddi_init_dp_buf_reg()
353 enum port port) in icl_calc_tbt_pll_link() argument
355 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()
377 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
380 pipe_config->hw.adjusted_mode.crtc_clock = in ddi_dotclock_get()
387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_set_dp_msa()
388 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_set_dp_msa()
389 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_set_dp_msa()
395 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
399 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
413 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
418 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
419 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_ddi_set_dp_msa()
421 if (crtc_state->limited_color_range) in intel_ddi_set_dp_msa()
429 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_ddi_set_dp_msa()
456 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_config_transcoder_dp2()
457 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_dp2()
476 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_transcoder_func_reg_val_get()
477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_transcoder_func_reg_val_get()
478 enum pipe pipe = crtc->pipe; in intel_ddi_transcoder_func_reg_val_get()
479 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_transcoder_func_reg_val_get()
480 enum port port = encoder->port; in intel_ddi_transcoder_func_reg_val_get() local
486 temp |= TGL_TRANS_DDI_SELECT_PORT(port); in intel_ddi_transcoder_func_reg_val_get()
488 temp |= TRANS_DDI_SELECT_PORT(port); in intel_ddi_transcoder_func_reg_val_get()
490 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
492 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
508 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) in intel_ddi_transcoder_func_reg_val_get()
510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) in intel_ddi_transcoder_func_reg_val_get()
519 /* On Haswell, can only use the always-on power well for in intel_ddi_transcoder_func_reg_val_get()
523 if (crtc_state->pch_pfit.force_thru) in intel_ddi_transcoder_func_reg_val_get()
538 if (crtc_state->has_hdmi_sink) in intel_ddi_transcoder_func_reg_val_get()
543 if (crtc_state->hdmi_scrambling) in intel_ddi_transcoder_func_reg_val_get()
545 if (crtc_state->hdmi_high_tmds_clock_ratio) in intel_ddi_transcoder_func_reg_val_get()
548 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
551 temp |= (crtc_state->fdi_lanes - 1) << 1; in intel_ddi_transcoder_func_reg_val_get()
557 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
562 master = crtc_state->mst_master_transcoder; in intel_ddi_transcoder_func_reg_val_get()
563 drm_WARN_ON(&dev_priv->drm, in intel_ddi_transcoder_func_reg_val_get()
569 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
573 crtc_state->master_transcoder != INVALID_TRANSCODER) { in intel_ddi_transcoder_func_reg_val_get()
575 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); in intel_ddi_transcoder_func_reg_val_get()
587 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_func()
588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_func()
589 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_func()
592 enum transcoder master_transcoder = crtc_state->master_transcoder; in intel_ddi_enable_transcoder_func()
620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_config_transcoder_func()
621 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_config_transcoder_func()
622 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_func()
632 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_disable_transcoder_func()
633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_disable_transcoder_func()
634 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_func()
643 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); in intel_ddi_disable_transcoder_func()
664 drm_dbg_kms(&dev_priv->drm, in intel_ddi_disable_transcoder_func()
675 struct drm_device *dev = intel_encoder->base.dev; in intel_ddi_toggle_hdcp_bits()
681 intel_encoder->power_domain); in intel_ddi_toggle_hdcp_bits()
683 return -ENXIO; in intel_ddi_toggle_hdcp_bits()
687 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_bits()
693 struct drm_device *dev = intel_connector->base.dev; in intel_ddi_connector_get_hw_state()
696 int type = intel_connector->base.connector_type; in intel_ddi_connector_get_hw_state()
697 enum port port = encoder->port; in intel_ddi_connector_get_hw_state() local
705 encoder->power_domain); in intel_ddi_connector_get_hw_state()
709 if (!encoder->get_hw_state(encoder, &pipe)) { in intel_ddi_connector_get_hw_state()
714 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_connector_get_hw_state()
753 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
761 struct drm_device *dev = encoder->base.dev; in intel_ddi_get_encoder_pipes()
763 enum port port = encoder->port; in intel_ddi_get_encoder_pipes() local
773 encoder->power_domain); in intel_ddi_get_encoder_pipes()
777 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
781 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { in intel_ddi_get_encoder_pipes()
817 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); in intel_ddi_get_encoder_pipes()
820 ddi_select = TRANS_DDI_SELECT_PORT(port); in intel_ddi_get_encoder_pipes()
840 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
842 encoder->base.base.id, encoder->base.name); in intel_ddi_get_encoder_pipes()
845 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
847 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
849 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
853 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
854 … "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", in intel_ddi_get_encoder_pipes()
855 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
862 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); in intel_ddi_get_encoder_pipes()
866 drm_err(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
868 encoder->base.base.id, encoder->base.name, tmp); in intel_ddi_get_encoder_pipes()
871 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
885 *pipe = ffs(pipe_mask) - 1; in intel_ddi_get_hw_state()
894 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_main_link_aux_domain()
895 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in intel_ddi_main_link_aux_domain()
901 * disabled. Accordingly use the AUX_IO_<port> power domain here which in intel_ddi_main_link_aux_domain()
906 * well, so we can acquire a wider AUX_<port> power domain reference in intel_ddi_main_link_aux_domain()
907 * instead of a specific AUX_IO_<port> reference without powering up any in intel_ddi_main_link_aux_domain()
910 if (intel_encoder_can_psr(&dig_port->base)) in intel_ddi_main_link_aux_domain()
911 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); in intel_ddi_main_link_aux_domain()
924 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_get()
928 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); in main_link_aux_power_domain_get()
933 dig_port->aux_wakeref = intel_display_power_get(i915, domain); in main_link_aux_power_domain_get()
940 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_put()
945 wf = fetch_and_zero(&dig_port->aux_wakeref); in main_link_aux_power_domain_put()
955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_power_domains()
960 * happen since fake-MST encoders don't set their get_power_domains() in intel_ddi_get_power_domains()
963 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_get_power_domains()
970 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_get_power_domains()
971 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_get_power_domains()
972 dig_port->ddi_io_power_domain); in intel_ddi_get_power_domains()
981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_clock()
982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_clock()
983 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_clock()
984 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_enable_transcoder_clock()
993 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
995 val = TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1002 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_disable_transcoder_clock()
1003 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_clock()
1018 enum port port, u8 iboost) in _skl_ddi_set_iboost() argument
1023 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); in _skl_ddi_set_iboost()
1025 tmp |= iboost << BALANCE_LEG_SHIFT(port); in _skl_ddi_set_iboost()
1027 tmp |= BALANCE_LEG_DISABLE(port); in _skl_ddi_set_iboost()
1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_ddi_set_iboost()
1040 iboost = intel_bios_hdmi_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1042 iboost = intel_bios_dp_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1048 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in skl_ddi_set_iboost()
1049 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in skl_ddi_set_iboost()
1052 iboost = trans->entries[level].hsw.i_boost; in skl_ddi_set_iboost()
1057 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
1061 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); in skl_ddi_set_iboost()
1063 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
1070 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_dp_voltage_max()
1071 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_dp_voltage_max()
1074 encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_dp_voltage_max()
1076 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
1078 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_dp_voltage_max()
1082 return index_to_dp_signal_levels[n_entries - 1] & in intel_ddi_dp_voltage_max()
1087 * We assume that the full set of pre-emphasis values can be
1099 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1102 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_ddi_combo_vswing_program()
1113 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_ddi_combo_vswing_program()
1117 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_ddi_combo_vswing_program()
1118 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_ddi_combo_vswing_program()
1125 intel_dp->hobl_active = is_hobl_buf_trans(trans); in icl_ddi_combo_vswing_program()
1127 intel_dp->hobl_active ? val : 0); in icl_ddi_combo_vswing_program()
1145 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1146 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1157 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | in icl_ddi_combo_vswing_program()
1158 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | in icl_ddi_combo_vswing_program()
1159 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); in icl_ddi_combo_vswing_program()
1168 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); in icl_ddi_combo_vswing_program()
1175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_combo_phy_set_signal_levels()
1176 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_combo_phy_set_signal_levels()
1181 * 1. If port type is eDP or DP, in icl_combo_phy_set_signal_levels()
1214 /* 5. Program swing and de-emphasis */ in icl_combo_phy_set_signal_levels()
1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_mg_phy_set_signal_levels()
1227 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_set_signal_levels()
1234 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_mg_phy_set_signal_levels()
1235 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_mg_phy_set_signal_levels()
1253 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1259 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1271 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1272 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1288 * Program MG_CLKHUB<LN, port being used> with value from frequency table in icl_mg_phy_set_signal_levels()
1295 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1298 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ in icl_mg_phy_set_signal_levels()
1303 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1310 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_dkl_phy_set_signal_levels()
1328 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in tgl_dkl_phy_set_signal_levels()
1335 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in tgl_dkl_phy_set_signal_levels()
1336 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in tgl_dkl_phy_set_signal_levels()
1350 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1351 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1352 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1360 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1361 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1362 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1402 drm_WARN(&i915->drm, 1, in translate_signal_level()
1403 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", in translate_signal_level()
1413 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level()
1429 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_level()
1433 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_level()
1434 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) in intel_ddi_level()
1443 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) in intel_ddi_level()
1444 level = n_entries - 1; in intel_ddi_level()
1453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_signal_levels()
1456 enum port port = encoder->port; in hsw_set_signal_levels() local
1468 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
1471 intel_dp->DP &= ~DDI_BUF_EMP_MASK; in hsw_set_signal_levels()
1472 intel_dp->DP |= signal_levels; in hsw_set_signal_levels()
1474 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1475 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
1481 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1491 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1497 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1501 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1524 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_enable_clock()
1525 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1526 enum phy phy = intel_port_to_phy(i915, encoder->port); in adls_ddi_enable_clock()
1528 if (drm_WARN_ON(&i915->drm, !pll)) in adls_ddi_enable_clock()
1533 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), in adls_ddi_enable_clock()
1539 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_disable_clock()
1540 enum phy phy = intel_port_to_phy(i915, encoder->port); in adls_ddi_disable_clock()
1548 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_is_clock_enabled()
1549 enum phy phy = intel_port_to_phy(i915, encoder->port); in adls_ddi_is_clock_enabled()
1557 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_get_pll()
1558 enum phy phy = intel_port_to_phy(i915, encoder->port); in adls_ddi_get_pll()
1568 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_enable_clock()
1569 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1570 enum phy phy = intel_port_to_phy(i915, encoder->port); in rkl_ddi_enable_clock()
1572 if (drm_WARN_ON(&i915->drm, !pll)) in rkl_ddi_enable_clock()
1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in rkl_ddi_enable_clock()
1583 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_disable_clock()
1584 enum phy phy = intel_port_to_phy(i915, encoder->port); in rkl_ddi_disable_clock()
1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_is_clock_enabled()
1593 enum phy phy = intel_port_to_phy(i915, encoder->port); in rkl_ddi_is_clock_enabled()
1601 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_get_pll()
1602 enum phy phy = intel_port_to_phy(i915, encoder->port); in rkl_ddi_get_pll()
1612 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_enable_clock()
1613 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1614 enum phy phy = intel_port_to_phy(i915, encoder->port); in dg1_ddi_enable_clock()
1616 if (drm_WARN_ON(&i915->drm, !pll)) in dg1_ddi_enable_clock()
1623 if (drm_WARN_ON(&i915->drm, in dg1_ddi_enable_clock()
1624 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || in dg1_ddi_enable_clock()
1625 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) in dg1_ddi_enable_clock()
1630 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in dg1_ddi_enable_clock()
1636 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_disable_clock()
1637 enum phy phy = intel_port_to_phy(i915, encoder->port); in dg1_ddi_disable_clock()
1645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_is_clock_enabled()
1646 enum phy phy = intel_port_to_phy(i915, encoder->port); in dg1_ddi_is_clock_enabled()
1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_get_pll()
1655 enum phy phy = intel_port_to_phy(i915, encoder->port); in dg1_ddi_get_pll()
1678 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_enable_clock()
1679 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1680 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_ddi_combo_enable_clock()
1682 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_combo_enable_clock()
1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in icl_ddi_combo_enable_clock()
1693 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_disable_clock()
1694 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_ddi_combo_disable_clock()
1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_is_clock_enabled()
1703 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_ddi_combo_is_clock_enabled()
1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_get_pll()
1712 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_ddi_combo_get_pll()
1722 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_enable_clock()
1723 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1724 enum port port = encoder->port; in jsl_ddi_tc_enable_clock() local
1726 if (drm_WARN_ON(&i915->drm, !pll)) in jsl_ddi_tc_enable_clock()
1730 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. in jsl_ddi_tc_enable_clock()
1733 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); in jsl_ddi_tc_enable_clock()
1740 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_disable_clock()
1741 enum port port = encoder->port; in jsl_ddi_tc_disable_clock() local
1745 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); in jsl_ddi_tc_disable_clock()
1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_is_clock_enabled()
1751 enum port port = encoder->port; in jsl_ddi_tc_is_clock_enabled() local
1754 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in jsl_ddi_tc_is_clock_enabled()
1765 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_enable_clock()
1766 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1767 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_enable_clock()
1768 enum port port = encoder->port; in icl_ddi_tc_enable_clock() local
1770 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_enable_clock()
1773 intel_de_write(i915, DDI_CLK_SEL(port), in icl_ddi_tc_enable_clock()
1776 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1781 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_disable_clock()
1787 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_disable_clock()
1788 enum port port = encoder->port; in icl_ddi_tc_disable_clock() local
1790 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1795 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1797 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); in icl_ddi_tc_disable_clock()
1802 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_is_clock_enabled()
1803 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_is_clock_enabled()
1804 enum port port = encoder->port; in icl_ddi_tc_is_clock_enabled() local
1807 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in icl_ddi_tc_is_clock_enabled()
1819 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_pll()
1820 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_get_pll()
1821 enum port port = encoder->port; in icl_ddi_tc_get_pll() local
1825 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in icl_ddi_tc_get_pll()
1849 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in bxt_ddi_get_pll()
1852 switch (encoder->port) { in bxt_ddi_get_pll()
1863 MISSING_CASE(encoder->port); in bxt_ddi_get_pll()
1873 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_enable_clock()
1874 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1875 enum port port = encoder->port; in skl_ddi_enable_clock() local
1877 if (drm_WARN_ON(&i915->drm, !pll)) in skl_ddi_enable_clock()
1880 mutex_lock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1883 DPLL_CTRL2_DDI_CLK_OFF(port) | in skl_ddi_enable_clock()
1884 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), in skl_ddi_enable_clock()
1885 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | in skl_ddi_enable_clock()
1886 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); in skl_ddi_enable_clock()
1888 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1893 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_disable_clock()
1894 enum port port = encoder->port; in skl_ddi_disable_clock() local
1896 mutex_lock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1899 0, DPLL_CTRL2_DDI_CLK_OFF(port)); in skl_ddi_disable_clock()
1901 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1906 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_is_clock_enabled()
1907 enum port port = encoder->port; in skl_ddi_is_clock_enabled() local
1913 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); in skl_ddi_is_clock_enabled()
1918 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_get_pll()
1919 enum port port = encoder->port; in skl_ddi_get_pll() local
1929 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) in skl_ddi_get_pll()
1932 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> in skl_ddi_get_pll()
1933 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); in skl_ddi_get_pll()
1941 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_enable_clock()
1942 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
1943 enum port port = encoder->port; in hsw_ddi_enable_clock() local
1945 if (drm_WARN_ON(&i915->drm, !pll)) in hsw_ddi_enable_clock()
1948 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); in hsw_ddi_enable_clock()
1953 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_disable_clock()
1954 enum port port = encoder->port; in hsw_ddi_disable_clock() local
1956 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); in hsw_ddi_disable_clock()
1961 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_is_clock_enabled()
1962 enum port port = encoder->port; in hsw_ddi_is_clock_enabled() local
1964 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; in hsw_ddi_is_clock_enabled()
1969 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_get_pll()
1970 enum port port = encoder->port; in hsw_ddi_get_pll() local
1974 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); in hsw_ddi_get_pll()
2008 if (encoder->enable_clock) in intel_ddi_enable_clock()
2009 encoder->enable_clock(encoder, crtc_state); in intel_ddi_enable_clock()
2014 if (encoder->disable_clock) in intel_ddi_disable_clock()
2015 encoder->disable_clock(encoder); in intel_ddi_disable_clock()
2020 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_sanitize_encoder_pll_mapping()
2028 if (encoder->type == INTEL_OUTPUT_DP_MST) in intel_ddi_sanitize_encoder_pll_mapping()
2031 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { in intel_ddi_sanitize_encoder_pll_mapping()
2040 if (drm_WARN_ON(&i915->drm, is_mst)) in intel_ddi_sanitize_encoder_pll_mapping()
2044 port_mask = BIT(encoder->port); in intel_ddi_sanitize_encoder_pll_mapping()
2045 ddi_clk_needed = encoder->base.crtc; in intel_ddi_sanitize_encoder_pll_mapping()
2047 if (encoder->type == INTEL_OUTPUT_DSI) { in intel_ddi_sanitize_encoder_pll_mapping()
2055 for_each_intel_encoder(&i915->drm, other_encoder) { in intel_ddi_sanitize_encoder_pll_mapping()
2059 if (drm_WARN_ON(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2060 port_mask & BIT(other_encoder->port))) in intel_ddi_sanitize_encoder_pll_mapping()
2070 if (ddi_clk_needed || !encoder->is_clock_enabled || in intel_ddi_sanitize_encoder_pll_mapping()
2071 !encoder->is_clock_enabled(encoder)) in intel_ddi_sanitize_encoder_pll_mapping()
2074 drm_notice(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2076 encoder->base.base.id, encoder->base.name); in intel_ddi_sanitize_encoder_pll_mapping()
2078 encoder->disable_clock(encoder); in intel_ddi_sanitize_encoder_pll_mapping()
2085 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_program_mg_dp_mode()
2086 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); in icl_program_mg_dp_mode()
2087 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in icl_program_mg_dp_mode()
2108 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2112 drm_WARN_ON(&dev_priv->drm, in icl_program_mg_dp_mode()
2170 return crtc_state->mst_master_transcoder; in tgl_dp_tp_transcoder()
2172 return crtc_state->cpu_transcoder; in tgl_dp_tp_transcoder()
2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_ctl_reg()
2183 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_status_reg()
2194 return DP_TP_STATUS(encoder->port); in dp_tp_status_reg()
2203 if (!crtc_state->vrr.enable) in intel_dp_sink_set_msa_timing_par_ignore_state()
2206 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, in intel_dp_sink_set_msa_timing_par_ignore_state()
2208 drm_dbg_kms(&i915->drm, in intel_dp_sink_set_msa_timing_par_ignore_state()
2219 if (!crtc_state->fec_enable) in intel_dp_sink_set_fec_ready()
2222 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, in intel_dp_sink_set_fec_ready()
2224 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", in intel_dp_sink_set_fec_ready()
2228 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, in intel_dp_sink_set_fec_ready()
2230 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); in intel_dp_sink_set_fec_ready()
2247 struct drm_i915_private *i915 = to_i915(aux->drm_dev); in wait_for_fec_detected()
2259 if (err == -ETIMEDOUT) in wait_for_fec_detected()
2260 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", in wait_for_fec_detected()
2263 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); in wait_for_fec_detected()
2270 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_wait_for_fec_status()
2274 if (!crtc_state->fec_enable) in intel_ddi_wait_for_fec_status()
2285 drm_err(&i915->drm, in intel_ddi_wait_for_fec_status()
2294 wait_for_fec_detected(&intel_dp->aux, enabled); in intel_ddi_wait_for_fec_status()
2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_enable_fec()
2302 if (!crtc_state->fec_enable) in intel_ddi_enable_fec()
2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_disable_fec()
2314 if (!crtc_state->fec_enable) in intel_ddi_disable_fec()
2325 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_power_up_lanes()
2327 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_power_up_lanes()
2331 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_ddi_power_up_lanes()
2334 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2351 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_mso_get_config()
2352 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_get_config()
2353 enum pipe pipe = crtc->pipe; in intel_ddi_mso_get_config()
2361 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()
2362 if (!pipe_config->splitter.enable) in intel_ddi_mso_get_config()
2365 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { in intel_ddi_mso_get_config()
2366 pipe_config->splitter.enable = false; in intel_ddi_mso_get_config()
2372 drm_WARN(&i915->drm, true, in intel_ddi_mso_get_config()
2376 pipe_config->splitter.link_count = 2; in intel_ddi_mso_get_config()
2379 pipe_config->splitter.link_count = 4; in intel_ddi_mso_get_config()
2383 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
2388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_mso_configure()
2389 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_configure()
2390 enum pipe pipe = crtc->pipe; in intel_ddi_mso_configure()
2396 if (crtc_state->splitter.enable) { in intel_ddi_mso_configure()
2398 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); in intel_ddi_mso_configure()
2399 if (crtc_state->splitter.link_count == 2) in intel_ddi_mso_configure()
2430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_enable_d2d()
2431 enum port port = encoder->port; in mtl_ddi_enable_d2d() local
2433 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0, in mtl_ddi_enable_d2d()
2436 if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & in mtl_ddi_enable_d2d()
2438 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2439 port_name(port)); in mtl_ddi_enable_d2d()
2446 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtl_port_buf_ctl_program()
2448 enum port port = encoder->port; in mtl_port_buf_ctl_program() local
2451 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)); in mtl_port_buf_ctl_program()
2453 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); in mtl_port_buf_ctl_program()
2461 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) in mtl_port_buf_ctl_program()
2464 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val); in mtl_port_buf_ctl_program()
2469 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtl_port_buf_ctl_io_selection()
2475 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), in mtl_port_buf_ctl_io_selection()
2488 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2489 crtc_state->lane_count); in mtl_ddi_pre_enable_dp()
2512 /* 5. Enable the port PLL */ in mtl_ddi_pre_enable_dp()
2516 * 6.a Configure Transcoder Clock Select to direct the Port clock to the in mtl_ddi_pre_enable_dp()
2522 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. in mtl_ddi_pre_enable_dp()
2543 to_intel_connector(conn_state->connector), in mtl_ddi_pre_enable_dp()
2558 * Train Display Port" step. Note that steps that are specific to in mtl_ddi_pre_enable_dp()
2562 * stream or multi-stream master transcoder" can just be performed in mtl_ddi_pre_enable_dp()
2571 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in mtl_ddi_pre_enable_dp()
2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_ddi_pre_enable_dp()
2599 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2600 crtc_state->lane_count); in tgl_ddi_pre_enable_dp()
2619 * 3. For non-TBT Type-C ports, set FIA lane count in tgl_ddi_pre_enable_dp()
2623 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). in tgl_ddi_pre_enable_dp()
2627 * 4. Enable the port PLL. in tgl_ddi_pre_enable_dp()
2630 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only in tgl_ddi_pre_enable_dp()
2631 * configure the PLL to port mapping here. in tgl_ddi_pre_enable_dp()
2637 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in tgl_ddi_pre_enable_dp()
2638 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in tgl_ddi_pre_enable_dp()
2639 dig_port->ddi_io_power_domain); in tgl_ddi_pre_enable_dp()
2647 * Train Display Port" step. Note that steps that are specific to in tgl_ddi_pre_enable_dp()
2651 * stream or multi-stream master transcoder" can just be performed in tgl_ddi_pre_enable_dp()
2656 * 7.a Configure Transcoder Clock Select to direct the Port clock to the in tgl_ddi_pre_enable_dp()
2679 encoder->set_signal_levels(encoder, crtc_state); in tgl_ddi_pre_enable_dp()
2698 to_intel_connector(conn_state->connector), in tgl_ddi_pre_enable_dp()
2713 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in tgl_ddi_pre_enable_dp()
2736 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_ddi_pre_enable_dp()
2737 enum port port = encoder->port; in hsw_ddi_pre_enable_dp() local
2742 drm_WARN_ON(&dev_priv->drm, in hsw_ddi_pre_enable_dp()
2743 is_mst && (port == PORT_A || port == PORT_E)); in hsw_ddi_pre_enable_dp()
2745 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2748 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
2749 crtc_state->lane_count); in hsw_ddi_pre_enable_dp()
2762 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in hsw_ddi_pre_enable_dp()
2763 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in hsw_ddi_pre_enable_dp()
2764 dig_port->ddi_io_power_domain); in hsw_ddi_pre_enable_dp()
2772 encoder->set_signal_levels(encoder, crtc_state); in hsw_ddi_pre_enable_dp()
2781 to_intel_connector(conn_state->connector), in hsw_ddi_pre_enable_dp()
2785 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && in hsw_ddi_pre_enable_dp()
2802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_dp()
2808 if (crtc_state->has_panel_replay) in intel_ddi_pre_enable_dp()
2809 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, in intel_ddi_pre_enable_dp()
2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_pre_enable_hdmi()
2834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_hdmi()
2839 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_pre_enable_hdmi()
2840 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_pre_enable_hdmi()
2841 dig_port->ddi_io_power_domain); in intel_ddi_pre_enable_hdmi()
2847 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable_hdmi()
2848 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
2857 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_enable()
2858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_pre_enable()
2859 enum pipe pipe = crtc->pipe; in intel_ddi_pre_enable()
2863 * - conn_state will be NULL in intel_ddi_pre_enable()
2864 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_pre_enable()
2865 * - the main connector associated with this port in intel_ddi_pre_enable()
2867 * - crtc_state will be the state of the first stream to in intel_ddi_pre_enable()
2868 * be activated on this port, and it may not be the same in intel_ddi_pre_enable()
2874 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
2889 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_pre_enable()
2890 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable()
2891 crtc_state->has_infoframe, in intel_ddi_pre_enable()
2899 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_disable_d2d_link()
2900 enum port port = encoder->port; in mtl_ddi_disable_d2d_link() local
2902 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), in mtl_ddi_disable_d2d_link()
2905 if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & in mtl_ddi_disable_d2d_link()
2907 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d_link()
2908 port_name(port)); in mtl_ddi_disable_d2d_link()
2914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_disable_ddi_buf()
2915 enum port port = encoder->port; in mtl_disable_ddi_buf() local
2919 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in mtl_disable_ddi_buf()
2922 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in mtl_disable_ddi_buf()
2925 mtl_wait_ddi_buf_idle(dev_priv, port); in mtl_disable_ddi_buf()
2941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in disable_ddi_buf()
2942 enum port port = encoder->port; in disable_ddi_buf() local
2946 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in disable_ddi_buf()
2949 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in disable_ddi_buf()
2960 intel_wait_ddi_buf_idle(dev_priv, port); in disable_ddi_buf()
2966 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_ddi_buf()
2985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_dp()
2987 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_post_disable_dp()
2997 * Power down sink before disabling the port, otherwise we end in intel_ddi_post_disable_dp()
3004 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_ddi_post_disable_dp()
3020 * From TGL spec: "If single stream or multi-stream master transcoder: in intel_ddi_post_disable_dp()
3030 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_dp()
3034 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_dp()
3039 /* De-select Thunderbolt */ in intel_ddi_post_disable_dp()
3041 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port), in intel_ddi_post_disable_dp()
3050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi()
3052 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_post_disable_hdmi()
3055 dig_port->set_infoframes(encoder, false, in intel_ddi_post_disable_hdmi()
3066 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_hdmi()
3069 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_hdmi()
3082 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable()
3100 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, in intel_ddi_post_disable()
3113 * - old_conn_state will be NULL in intel_ddi_post_disable()
3114 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_post_disable()
3115 * - the main connector associated with this port in intel_ddi_post_disable()
3117 * - old_crtc_state will be the state of the last stream to in intel_ddi_post_disable()
3118 * be deactivated on this port, and it may not be the same in intel_ddi_post_disable()
3137 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_post_pll_disable()
3139 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_post_pll_disable()
3156 if (!crtc_state->sync_mode_slaves_mask) in trans_port_sync_stop_link_train()
3159 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in trans_port_sync_stop_link_train()
3161 to_intel_encoder(conn_state->best_encoder); in trans_port_sync_stop_link_train()
3162 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); in trans_port_sync_stop_link_train()
3171 if (slave_crtc_state->master_transcoder != in trans_port_sync_stop_link_train()
3172 crtc_state->cpu_transcoder) in trans_port_sync_stop_link_train()
3190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_dp()
3193 enum port port = encoder->port; in intel_enable_ddi_dp() local
3195 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) in intel_enable_ddi_dp()
3201 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_enable_ddi_dp()
3218 enum port port) in gen9_chicken_trans_reg_by_port() argument
3228 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); in gen9_chicken_trans_reg_by_port()
3230 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3231 port = PORT_A; in gen9_chicken_trans_reg_by_port()
3233 return CHICKEN_TRANS(trans[port]); in gen9_chicken_trans_reg_by_port()
3241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_hdmi()
3243 struct drm_connector *connector = conn_state->connector; in intel_enable_ddi_hdmi()
3244 enum port port = encoder->port; in intel_enable_ddi_hdmi() local
3245 enum phy phy = intel_port_to_phy(dev_priv, port); in intel_enable_ddi_hdmi()
3249 crtc_state->hdmi_high_tmds_clock_ratio, in intel_enable_ddi_hdmi()
3250 crtc_state->hdmi_scrambling)) in intel_enable_ddi_hdmi()
3251 drm_dbg_kms(&dev_priv->drm, in intel_enable_ddi_hdmi()
3253 connector->base.id, connector->name); in intel_enable_ddi_hdmi()
3262 encoder->set_signal_levels(encoder, crtc_state); in intel_enable_ddi_hdmi()
3269 * the bits affect a specific DDI port rather than in intel_enable_ddi_hdmi()
3272 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); in intel_enable_ddi_hdmi()
3277 if (port == PORT_E) in intel_enable_ddi_hdmi()
3289 if (port == PORT_E) in intel_enable_ddi_hdmi()
3301 /* In HDMI/DVI mode, the port width, and swing/emphasis values in intel_enable_ddi_hdmi()
3303 * enabling the port. in intel_enable_ddi_hdmi()
3312 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; in intel_enable_ddi_hdmi()
3314 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); in intel_enable_ddi_hdmi()
3319 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) in intel_enable_ddi_hdmi()
3322 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), in intel_enable_ddi_hdmi()
3327 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); in intel_enable_ddi_hdmi()
3331 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); in intel_enable_ddi_hdmi()
3333 intel_wait_ddi_buf_active(dev_priv, port); in intel_enable_ddi_hdmi()
3341 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in intel_enable_ddi()
3371 to_intel_connector(old_conn_state->connector); in intel_disable_ddi_dp()
3373 intel_dp->link_trained = false; in intel_disable_ddi_dp()
3390 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_disable_ddi_hdmi()
3391 struct drm_connector *connector = old_conn_state->connector; in intel_disable_ddi_hdmi()
3395 drm_dbg_kms(&i915->drm, in intel_disable_ddi_hdmi()
3397 connector->base.id, connector->name); in intel_disable_ddi_hdmi()
3407 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); in intel_disable_ddi()
3448 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_update_active_dpll()
3452 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_update_active_dpll()
3459 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in intel_ddi_update_active_dpll()
3470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_pll_enable()
3472 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_pre_pll_enable()
3477 to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_pll_enable()
3479 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3488 * Type-C ports. Skip this step for TBT. in intel_ddi_pre_pll_enable()
3490 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3493 crtc_state->lane_lat_optim_mask); in intel_ddi_pre_pll_enable()
3498 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_tbt_to_dp_alt_switch_wa()
3499 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in adlp_tbt_to_dp_alt_switch_wa()
3510 struct intel_encoder *encoder = &dig_port->base; in mtl_ddi_prepare_link_retrain()
3511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_prepare_link_retrain()
3512 enum port port = encoder->port; in mtl_ddi_prepare_link_retrain() local
3517 * necessary disable and enable port in mtl_ddi_prepare_link_retrain()
3529 if (crtc_state->enhanced_framing) in mtl_ddi_prepare_link_retrain()
3539 encoder->set_signal_levels(encoder, crtc_state); in mtl_ddi_prepare_link_retrain()
3544 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ in mtl_ddi_prepare_link_retrain()
3545 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in mtl_ddi_prepare_link_retrain()
3546 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in mtl_ddi_prepare_link_retrain()
3547 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in mtl_ddi_prepare_link_retrain()
3550 intel_wait_ddi_buf_active(dev_priv, port); in mtl_ddi_prepare_link_retrain()
3557 struct intel_encoder *encoder = &dig_port->base; in intel_ddi_prepare_link_retrain()
3558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_prepare_link_retrain()
3559 enum port port = encoder->port; in intel_ddi_prepare_link_retrain() local
3566 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
3568 intel_de_write(dev_priv, DDI_BUF_CTL(port), in intel_ddi_prepare_link_retrain()
3578 intel_wait_ddi_buf_idle(dev_priv, port); in intel_ddi_prepare_link_retrain()
3586 if (crtc_state->enhanced_framing) in intel_ddi_prepare_link_retrain()
3596 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
3597 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in intel_ddi_prepare_link_retrain()
3598 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
3600 intel_wait_ddi_buf_active(dev_priv, port); in intel_ddi_prepare_link_retrain()
3607 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_link_train()
3608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_link_train()
3638 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_idle_link_train()
3639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_idle_link_train()
3640 enum port port = encoder->port; in intel_ddi_set_idle_link_train() local
3648 * issue where we enable the pipe while not in idle link-training mode. in intel_ddi_set_idle_link_train()
3652 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) in intel_ddi_set_idle_link_train()
3658 drm_err(&dev_priv->drm, in intel_ddi_set_idle_link_train()
3677 if (crtc_state->port_clock > 594000) in tgl_ddi_min_voltage_level()
3685 if (crtc_state->port_clock > 594000) in jsl_ddi_min_voltage_level()
3693 if (crtc_state->port_clock > 594000) in icl_ddi_min_voltage_level()
3701 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_compute_min_voltage_level()
3704 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3706 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3708 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3710 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3737 return master_select - 1; in bdw_transcoder_master_readout()
3742 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in bdw_get_trans_port_sync_config()
3747 crtc_state->master_transcoder = in bdw_get_trans_port_sync_config()
3748 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
3762 crtc_state->cpu_transcoder) in bdw_get_trans_port_sync_config()
3763 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); in bdw_get_trans_port_sync_config()
3768 drm_WARN_ON(&dev_priv->drm, in bdw_get_trans_port_sync_config()
3769 crtc_state->master_transcoder != INVALID_TRANSCODER && in bdw_get_trans_port_sync_config()
3770 crtc_state->sync_mode_slaves_mask); in bdw_get_trans_port_sync_config()
3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_read_func_ctl()
3777 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_read_func_ctl()
3778 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_read_func_ctl()
3792 pipe_config->hw.adjusted_mode.flags |= flags; in intel_ddi_read_func_ctl()
3796 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3799 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3802 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3805 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3813 pipe_config->has_hdmi_sink = true; in intel_ddi_read_func_ctl()
3815 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3818 if (pipe_config->infoframes.enable) in intel_ddi_read_func_ctl()
3819 pipe_config->has_infoframe = true; in intel_ddi_read_func_ctl()
3822 pipe_config->hdmi_scrambling = true; in intel_ddi_read_func_ctl()
3824 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_ddi_read_func_ctl()
3827 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_read_func_ctl()
3829 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3832 pipe_config->lane_count = 4; in intel_ddi_read_func_ctl()
3835 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_read_func_ctl()
3836 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_read_func_ctl()
3838 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_read_func_ctl()
3839 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3843 &pipe_config->dp_m_n); in intel_ddi_read_func_ctl()
3845 &pipe_config->dp_m2_n2); in intel_ddi_read_func_ctl()
3847 pipe_config->enhanced_framing = in intel_ddi_read_func_ctl()
3852 pipe_config->fec_enable = in intel_ddi_read_func_ctl()
3856 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_read_func_ctl()
3857 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3860 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3866 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_read_func_ctl()
3867 pipe_config->enhanced_framing = in intel_ddi_read_func_ctl()
3874 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_read_func_ctl()
3875 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3879 pipe_config->mst_master_transcoder = in intel_ddi_read_func_ctl()
3883 &pipe_config->dp_m_n); in intel_ddi_read_func_ctl()
3886 pipe_config->fec_enable = in intel_ddi_read_func_ctl()
3890 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_config()
3902 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
3905 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
3912 pipe_config->has_audio = in intel_ddi_get_config()
3915 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_get_config()
3916 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
3921 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
3930 &pipe_config->infoframes.avi); in intel_ddi_get_config()
3933 &pipe_config->infoframes.spd); in intel_ddi_get_config()
3936 &pipe_config->infoframes.hdmi); in intel_ddi_get_config()
3939 &pipe_config->infoframes.drm); in intel_ddi_get_config()
3956 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_get_clock()
3958 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in intel_ddi_get_clock()
3961 if (drm_WARN_ON(&i915->drm, !pll)) in intel_ddi_get_clock()
3964 port_dpll->pll = pll; in intel_ddi_get_clock()
3965 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in intel_ddi_get_clock()
3966 drm_WARN_ON(&i915->drm, !pll_active); in intel_ddi_get_clock()
3970 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3971 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
3980 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); in mtl_ddi_get_config()
3982 intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state); in mtl_ddi_get_config()
3983 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); in mtl_ddi_get_config()
3992 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); in dg2_ddi_get_config()
3993 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); in dg2_ddi_get_config()
4028 return pll->info->id == DPLL_ID_ICL_TBTPLL; in icl_ddi_tc_pll_is_tbt()
4035 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_port_pll_type()
4036 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_port_pll_type()
4038 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_port_pll_type()
4051 if (!encoder->port_pll_type) in intel_ddi_port_pll_type()
4054 return encoder->port_pll_type(encoder, crtc_state); in intel_ddi_port_pll_type()
4061 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_clock()
4066 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_get_clock()
4074 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in icl_ddi_tc_get_clock()
4076 port_dpll->pll = pll; in icl_ddi_tc_get_clock()
4077 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in icl_ddi_tc_get_clock()
4078 drm_WARN_ON(&i915->drm, !pll_active); in icl_ddi_tc_get_clock()
4082 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) in icl_ddi_tc_get_clock()
4083 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); in icl_ddi_tc_get_clock()
4085 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
4086 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
4120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_sync_state()
4121 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_sync_state()
4134 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_initial_fastset_check()
4135 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_initial_fastset_check()
4139 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
4140 encoder->base.base.id, encoder->base.name); in intel_ddi_initial_fastset_check()
4141 crtc_state->uapi.mode_changed = true; in intel_ddi_initial_fastset_check()
4157 switch (conn_state->connector->connector_type) { in intel_ddi_compute_output_type()
4165 MISSING_CASE(conn_state->connector->connector_type); in intel_ddi_compute_output_type()
4174 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_compute_config()
4175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_compute_config()
4176 enum port port = encoder->port; in intel_ddi_compute_config() local
4179 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_compute_config()
4180 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
4183 pipe_config->has_hdmi_sink = in intel_ddi_compute_config()
4194 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4195 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_ddi_compute_config()
4196 pipe_config->pch_pfit.force_thru = in intel_ddi_compute_config()
4197 pipe_config->pch_pfit.enabled || in intel_ddi_compute_config()
4198 pipe_config->crc_enabled; in intel_ddi_compute_config()
4201 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
4202 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
4216 mode1->clock == mode2->clock; /* we want an exact match */ in mode_equal()
4222 return m_n_1->tu == m_n_2->tu && in m_n_equal()
4223 m_n_1->data_m == m_n_2->data_m && in m_n_equal()
4224 m_n_1->data_n == m_n_2->data_n && in m_n_equal()
4225 m_n_1->link_m == m_n_2->link_m && in m_n_equal()
4226 m_n_1->link_n == m_n_2->link_n; in m_n_equal()
4232 return crtc_state1->hw.active && crtc_state2->hw.active && in crtcs_port_sync_compatible()
4233 crtc_state1->output_types == crtc_state2->output_types && in crtcs_port_sync_compatible()
4234 crtc_state1->output_format == crtc_state2->output_format && in crtcs_port_sync_compatible()
4235 crtc_state1->lane_count == crtc_state2->lane_count && in crtcs_port_sync_compatible()
4236 crtc_state1->port_clock == crtc_state2->port_clock && in crtcs_port_sync_compatible()
4237 mode_equal(&crtc_state1->hw.adjusted_mode, in crtcs_port_sync_compatible()
4238 &crtc_state2->hw.adjusted_mode) && in crtcs_port_sync_compatible()
4239 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
4248 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); in intel_ddi_port_sync_transcoders()
4250 to_intel_atomic_state(ref_crtc_state->uapi.state); in intel_ddi_port_sync_transcoders()
4255 * We don't enable port sync on BDW due to missing w/as and in intel_ddi_port_sync_transcoders()
4264 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { in intel_ddi_port_sync_transcoders()
4265 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_ddi_port_sync_transcoders()
4271 if (!connector->has_tile || in intel_ddi_port_sync_transcoders()
4272 connector->tile_group->id != in intel_ddi_port_sync_transcoders()
4280 transcoders |= BIT(crtc_state->cpu_transcoder); in intel_ddi_port_sync_transcoders()
4290 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_compute_config_late()
4291 struct drm_connector *connector = conn_state->connector; in intel_ddi_compute_config_late()
4294 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", in intel_ddi_compute_config_late()
4295 encoder->base.base.id, encoder->base.name, in intel_ddi_compute_config_late()
4296 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
4298 if (connector->has_tile) in intel_ddi_compute_config_late()
4300 connector->tile_group->id); in intel_ddi_compute_config_late()
4307 crtc_state->master_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config_late()
4309 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; in intel_ddi_compute_config_late()
4311 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
4312 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_ddi_compute_config_late()
4313 crtc_state->sync_mode_slaves_mask = in intel_ddi_compute_config_late()
4314 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); in intel_ddi_compute_config_late()
4322 struct drm_i915_private *i915 = to_i915(encoder->dev); in intel_ddi_encoder_destroy()
4324 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in intel_ddi_encoder_destroy()
4332 kfree(dig_port->hdcp_port_data.streams); in intel_ddi_encoder_destroy()
4338 struct drm_i915_private *i915 = to_i915(encoder->dev); in intel_ddi_encoder_reset()
4341 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in intel_ddi_encoder_reset()
4343 intel_dp->reset_link_params = true; in intel_ddi_encoder_reset()
4369 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_init_dp_connector()
4371 enum port port = dig_port->base.port; in intel_ddi_init_dp_connector() local
4377 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4379 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4381 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4382 dig_port->dp.set_link_train = intel_ddi_set_link_train; in intel_ddi_init_dp_connector()
4383 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; in intel_ddi_init_dp_connector()
4385 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; in intel_ddi_init_dp_connector()
4386 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; in intel_ddi_init_dp_connector()
4393 if (dig_port->base.type == INTEL_OUTPUT_EDP) { in intel_ddi_init_dp_connector()
4394 struct drm_device *dev = dig_port->base.base.dev; in intel_ddi_init_dp_connector()
4397 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); in intel_ddi_init_dp_connector()
4399 drm_connector_attach_privacy_screen_provider(&connector->base, in intel_ddi_init_dp_connector()
4401 } else if (PTR_ERR(privacy_screen) != -ENODEV) { in intel_ddi_init_dp_connector()
4402 drm_warn(dev, "Error getting privacy-screen\n"); in intel_ddi_init_dp_connector()
4416 state = drm_atomic_state_alloc(crtc->dev); in modeset_pipe()
4418 return -ENOMEM; in modeset_pipe()
4420 state->acquire_ctx = ctx; in modeset_pipe()
4421 to_intel_atomic_state(state)->internal = true; in modeset_pipe()
4429 crtc_state->connectors_changed = true; in modeset_pipe()
4441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_reset_link()
4443 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_reset_link()
4444 struct i2c_adapter *ddc = connector->base.ddc; in intel_hdmi_reset_link()
4451 if (connector->base.status != connector_status_connected) in intel_hdmi_reset_link()
4454 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_hdmi_reset_link()
4459 conn_state = connector->base.state; in intel_hdmi_reset_link()
4461 crtc = to_intel_crtc(conn_state->crtc); in intel_hdmi_reset_link()
4465 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_hdmi_reset_link()
4469 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
4471 drm_WARN_ON(&dev_priv->drm, in intel_hdmi_reset_link()
4474 if (!crtc_state->hw.active) in intel_hdmi_reset_link()
4477 if (!crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4478 !crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4481 if (conn_state->commit && in intel_hdmi_reset_link()
4482 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_hdmi_reset_link()
4487 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4488 connector->base.base.id, connector->base.name, ret); in intel_hdmi_reset_link()
4493 crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4495 crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4507 return modeset_pipe(&crtc->base, ctx); in intel_hdmi_reset_link()
4514 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_hotplug()
4516 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_hotplug()
4517 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_hotplug()
4523 if (intel_dp->compliance.test_active && in intel_ddi_hotplug()
4524 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { in intel_ddi_hotplug()
4534 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) in intel_ddi_hotplug()
4540 drm_WARN_ON(encoder->base.dev, ret); in intel_ddi_hotplug()
4544 * Unpowered type-c dongles can take some time to boot and be in intel_ddi_hotplug()
4559 * Type-c connectors which get their HPD signal deasserted then in intel_ddi_hotplug()
4562 * becomes functional. Retry the detection for 5 seconds on type-c in intel_ddi_hotplug()
4566 connector->hotplug_retries < (is_tc ? 5 : 1) && in intel_ddi_hotplug()
4567 !dig_port->dp.is_mst) in intel_ddi_hotplug()
4575 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in lpt_digital_port_connected()
4576 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4583 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_digital_port_connected()
4584 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bdw_digital_port_connected()
4592 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4601 enum port port = dig_port->base.port; in intel_ddi_init_hdmi_connector() local
4607 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4615 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_a_force_4_lanes()
4617 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4620 if (dig_port->saved_port_bits & DDI_A_4_LANES) in intel_ddi_a_force_4_lanes()
4635 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_max_lanes()
4636 enum port port = dig_port->base.port; in intel_ddi_max_lanes() local
4642 if (port == PORT_A || port == PORT_E) { in intel_ddi_max_lanes()
4644 max_lanes = port == PORT_A ? 4 : 0; in intel_ddi_max_lanes()
4651 * Some BIOS might fail to set this bit on port A if eDP in intel_ddi_max_lanes()
4656 drm_dbg_kms(&dev_priv->drm, in intel_ddi_max_lanes()
4657 "Forcing DDI_A_4_LANES for port A\n"); in intel_ddi_max_lanes()
4658 dig_port->saved_port_bits |= DDI_A_4_LANES; in intel_ddi_max_lanes()
4666 enum port port) in xelpd_hpd_pin() argument
4668 if (port >= PORT_D_XELPD) in xelpd_hpd_pin()
4669 return HPD_PORT_D + port - PORT_D_XELPD; in xelpd_hpd_pin()
4670 else if (port >= PORT_TC1) in xelpd_hpd_pin()
4671 return HPD_PORT_TC1 + port - PORT_TC1; in xelpd_hpd_pin()
4673 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4677 enum port port) in dg1_hpd_pin() argument
4679 if (port >= PORT_TC1) in dg1_hpd_pin()
4680 return HPD_PORT_C + port - PORT_TC1; in dg1_hpd_pin()
4682 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4686 enum port port) in tgl_hpd_pin() argument
4688 if (port >= PORT_TC1) in tgl_hpd_pin()
4689 return HPD_PORT_TC1 + port - PORT_TC1; in tgl_hpd_pin()
4691 return HPD_PORT_A + port - PORT_A; in tgl_hpd_pin()
4695 enum port port) in rkl_hpd_pin() argument
4698 return tgl_hpd_pin(dev_priv, port); in rkl_hpd_pin()
4700 if (port >= PORT_TC1) in rkl_hpd_pin()
4701 return HPD_PORT_C + port - PORT_TC1; in rkl_hpd_pin()
4703 return HPD_PORT_A + port - PORT_A; in rkl_hpd_pin()
4707 enum port port) in icl_hpd_pin() argument
4709 if (port >= PORT_C) in icl_hpd_pin()
4710 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
4712 return HPD_PORT_A + port - PORT_A; in icl_hpd_pin()
4716 enum port port) in ehl_hpd_pin() argument
4718 if (port == PORT_D) in ehl_hpd_pin()
4722 return icl_hpd_pin(dev_priv, port); in ehl_hpd_pin()
4724 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4727 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) in skl_hpd_pin() argument
4730 return icl_hpd_pin(dev_priv, port); in skl_hpd_pin()
4732 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
4735 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) in intel_ddi_is_tc() argument
4738 return port >= PORT_TC1; in intel_ddi_is_tc()
4740 return port >= PORT_C; in intel_ddi_is_tc()
4772 #define port_tc_name(port) ((port) - PORT_TC1 + '1') argument
4773 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4775 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) in port_strap_detected() argument
4781 switch (port) { in port_strap_detected()
4791 return true; /* no strap for DDI-E */ in port_strap_detected()
4793 MISSING_CASE(port); in port_strap_detected()
4800 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in need_aux_ch()
4801 enum phy phy = intel_port_to_phy(i915, encoder->port); in need_aux_ch()
4808 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && in assert_has_icl_dsi()
4813 static bool port_in_use(struct drm_i915_private *i915, enum port port) in port_in_use() argument
4817 for_each_intel_encoder(&i915->drm, encoder) { in port_in_use()
4818 /* FIXME what about second port for dual link DSI? */ in port_in_use()
4819 if (encoder->port == port) in port_in_use()
4832 enum port port; in intel_ddi_init() local
4835 port = intel_bios_encoder_port(devdata); in intel_ddi_init()
4836 if (port == PORT_NONE) in intel_ddi_init()
4839 if (!port_strap_detected(dev_priv, port)) { in intel_ddi_init()
4840 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4841 "Port %c strap not detected\n", port_name(port)); in intel_ddi_init()
4845 if (!assert_port_valid(dev_priv, port)) in intel_ddi_init()
4848 if (port_in_use(dev_priv, port)) { in intel_ddi_init()
4849 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4850 "Port %c already claimed\n", port_name(port)); in intel_ddi_init()
4863 phy = intel_port_to_phy(dev_priv, port); in intel_ddi_init()
4872 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
4873 port_name(port), phy_name(phy)); in intel_ddi_init()
4889 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
4890 port_name(port)); in intel_ddi_init()
4894 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4895 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", in intel_ddi_init()
4896 port_name(port)); in intel_ddi_init()
4901 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
4902 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4911 dig_port->aux_ch = AUX_CH_NONE; in intel_ddi_init()
4913 encoder = &dig_port->base; in intel_ddi_init()
4914 encoder->devdata = devdata; in intel_ddi_init()
4916 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { in intel_ddi_init()
4917 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4920 port_name(port - PORT_D_XELPD + PORT_D), in intel_ddi_init()
4923 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init()
4925 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4928 port >= PORT_TC1 ? "TC" : "", in intel_ddi_init()
4929 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), in intel_ddi_init()
4933 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init()
4935 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4938 port_name(port), in intel_ddi_init()
4939 port >= PORT_C ? " (TC)" : "", in intel_ddi_init()
4943 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4945 "DDI %c/PHY %c", port_name(port), phy_name(phy)); in intel_ddi_init()
4948 mutex_init(&dig_port->hdcp_mutex); in intel_ddi_init()
4949 dig_port->num_hdcp_streams = 0; in intel_ddi_init()
4951 encoder->hotplug = intel_ddi_hotplug; in intel_ddi_init()
4952 encoder->compute_output_type = intel_ddi_compute_output_type; in intel_ddi_init()
4953 encoder->compute_config = intel_ddi_compute_config; in intel_ddi_init()
4954 encoder->compute_config_late = intel_ddi_compute_config_late; in intel_ddi_init()
4955 encoder->enable = intel_enable_ddi; in intel_ddi_init()
4956 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; in intel_ddi_init()
4957 encoder->pre_enable = intel_ddi_pre_enable; in intel_ddi_init()
4958 encoder->disable = intel_disable_ddi; in intel_ddi_init()
4959 encoder->post_pll_disable = intel_ddi_post_pll_disable; in intel_ddi_init()
4960 encoder->post_disable = intel_ddi_post_disable; in intel_ddi_init()
4961 encoder->update_pipe = intel_ddi_update_pipe; in intel_ddi_init()
4962 encoder->audio_enable = intel_audio_codec_enable; in intel_ddi_init()
4963 encoder->audio_disable = intel_audio_codec_disable; in intel_ddi_init()
4964 encoder->get_hw_state = intel_ddi_get_hw_state; in intel_ddi_init()
4965 encoder->sync_state = intel_ddi_sync_state; in intel_ddi_init()
4966 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; in intel_ddi_init()
4967 encoder->suspend = intel_ddi_encoder_suspend; in intel_ddi_init()
4968 encoder->shutdown = intel_ddi_encoder_shutdown; in intel_ddi_init()
4969 encoder->get_power_domains = intel_ddi_get_power_domains; in intel_ddi_init()
4971 encoder->type = INTEL_OUTPUT_DDI; in intel_ddi_init()
4972 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); in intel_ddi_init()
4973 encoder->port = port; in intel_ddi_init()
4974 encoder->cloneable = 0; in intel_ddi_init()
4975 encoder->pipe_mask = ~0; in intel_ddi_init()
4978 encoder->enable_clock = intel_mtl_pll_enable; in intel_ddi_init()
4979 encoder->disable_clock = intel_mtl_pll_disable; in intel_ddi_init()
4980 encoder->port_pll_type = intel_mtl_port_pll_type; in intel_ddi_init()
4981 encoder->get_config = mtl_ddi_get_config; in intel_ddi_init()
4983 encoder->enable_clock = intel_mpllb_enable; in intel_ddi_init()
4984 encoder->disable_clock = intel_mpllb_disable; in intel_ddi_init()
4985 encoder->get_config = dg2_ddi_get_config; in intel_ddi_init()
4987 encoder->enable_clock = adls_ddi_enable_clock; in intel_ddi_init()
4988 encoder->disable_clock = adls_ddi_disable_clock; in intel_ddi_init()
4989 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; in intel_ddi_init()
4990 encoder->get_config = adls_ddi_get_config; in intel_ddi_init()
4992 encoder->enable_clock = rkl_ddi_enable_clock; in intel_ddi_init()
4993 encoder->disable_clock = rkl_ddi_disable_clock; in intel_ddi_init()
4994 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; in intel_ddi_init()
4995 encoder->get_config = rkl_ddi_get_config; in intel_ddi_init()
4997 encoder->enable_clock = dg1_ddi_enable_clock; in intel_ddi_init()
4998 encoder->disable_clock = dg1_ddi_disable_clock; in intel_ddi_init()
4999 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; in intel_ddi_init()
5000 encoder->get_config = dg1_ddi_get_config; in intel_ddi_init()
5002 if (intel_ddi_is_tc(dev_priv, port)) { in intel_ddi_init()
5003 encoder->enable_clock = jsl_ddi_tc_enable_clock; in intel_ddi_init()
5004 encoder->disable_clock = jsl_ddi_tc_disable_clock; in intel_ddi_init()
5005 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5006 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5007 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5009 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5010 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5011 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5012 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5015 if (intel_ddi_is_tc(dev_priv, port)) { in intel_ddi_init()
5016 encoder->enable_clock = icl_ddi_tc_enable_clock; in intel_ddi_init()
5017 encoder->disable_clock = icl_ddi_tc_disable_clock; in intel_ddi_init()
5018 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5019 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5020 encoder->get_config = icl_ddi_tc_get_config; in intel_ddi_init()
5022 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5023 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5024 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5025 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5028 /* BXT/GLK have fixed PLL->port mapping */ in intel_ddi_init()
5029 encoder->get_config = bxt_ddi_get_config; in intel_ddi_init()
5031 encoder->enable_clock = skl_ddi_enable_clock; in intel_ddi_init()
5032 encoder->disable_clock = skl_ddi_disable_clock; in intel_ddi_init()
5033 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; in intel_ddi_init()
5034 encoder->get_config = skl_ddi_get_config; in intel_ddi_init()
5036 encoder->enable_clock = hsw_ddi_enable_clock; in intel_ddi_init()
5037 encoder->disable_clock = hsw_ddi_disable_clock; in intel_ddi_init()
5038 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_ddi_init()
5039 encoder->get_config = hsw_ddi_get_config; in intel_ddi_init()
5043 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; in intel_ddi_init()
5045 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; in intel_ddi_init()
5048 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5050 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; in intel_ddi_init()
5053 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5055 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; in intel_ddi_init()
5057 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; in intel_ddi_init()
5059 encoder->set_signal_levels = hsw_set_signal_levels; in intel_ddi_init()
5065 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); in intel_ddi_init()
5067 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); in intel_ddi_init()
5069 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); in intel_ddi_init()
5071 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); in intel_ddi_init()
5073 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); in intel_ddi_init()
5075 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); in intel_ddi_init()
5077 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); in intel_ddi_init()
5079 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); in intel_ddi_init()
5082 dig_port->saved_port_bits = in intel_ddi_init()
5083 intel_de_read(dev_priv, DDI_BUF_CTL(port)) in intel_ddi_init()
5086 dig_port->saved_port_bits = in intel_ddi_init()
5087 intel_de_read(dev_priv, DDI_BUF_CTL(port)) in intel_ddi_init()
5091 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; in intel_ddi_init()
5093 dig_port->dp.output_reg = INVALID_MMIO_REG; in intel_ddi_init()
5094 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
5097 dig_port->aux_ch = intel_dp_aux_ch(encoder); in intel_ddi_init()
5098 if (dig_port->aux_ch == AUX_CH_NONE) in intel_ddi_init()
5110 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5111 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", in intel_ddi_init()
5112 port_name(port), in intel_ddi_init()
5114 is_legacy ? "legacy" : "non-legacy"); in intel_ddi_init()
5117 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; in intel_ddi_init()
5118 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; in intel_ddi_init()
5124 drm_WARN_ON(&dev_priv->drm, port > PORT_I); in intel_ddi_init()
5125 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); in intel_ddi_init()
5129 dig_port->connected = intel_tc_port_connected; in intel_ddi_init()
5131 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5133 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5135 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5137 if (port == PORT_A) in intel_ddi_init()
5138 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5140 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5142 if (port == PORT_A) in intel_ddi_init()
5143 dig_port->connected = hsw_digital_port_connected; in intel_ddi_init()
5145 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5154 dig_port->hpd_pulse = intel_dp_hpd_pulse; in intel_ddi_init()
5156 if (dig_port->dp.mso_link_count) in intel_ddi_init()
5157 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); in intel_ddi_init()
5161 * In theory we don't need the encoder->type check, in intel_ddi_init()
5164 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { in intel_ddi_init()
5172 drm_encoder_cleanup(&encoder->base); in intel_ddi_init()