115  * Starting with Haswell, DDI port buffers must be programmed with correct
146  * Starting with Haswell, DDI port buffers must be programmed with correct
184 		drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",  in mtl_wait_ddi_buf_idle()
198 		drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",  in intel_wait_ddi_buf_idle()
236 		drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",  in intel_wait_ddi_buf_active()
665 			    "Quirk Increase DDI disabled time\n");  in intel_ddi_disable_transcoder_func()
1088  * used on all DDI platforms. Should that change we need to
2064 		 * For DSI we keep the ddi clocks gated  in intel_ddi_sanitize_encoder_pll_mapping()
2075 		   "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",  in intel_ddi_sanitize_encoder_pll_mapping()
2527 	 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST  in mtl_ddi_pre_enable_dp()
2547 	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit  in mtl_ddi_pre_enable_dp()
2665 	 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST  in tgl_ddi_pre_enable_dp()
2683 	 * the used lanes of the DDI.  in tgl_ddi_pre_enable_dp()
2701 	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit  in tgl_ddi_pre_enable_dp()
3269 		 * the bits affect a specific DDI port rather than  in intel_enable_ddi_hdmi()
4791 		return true; /* no strap for DDI-E */  in port_strap_detected()
4919 				 "DDI %c/PHY %c",  in intel_ddi_init()
4927 				 "DDI %s%c/PHY %s%c",  in intel_ddi_init()
4937 				 "DDI %c%s/PHY %s%c",  in intel_ddi_init()
4945 				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));  in intel_ddi_init()