Lines Matching +full:1 +full:gbps
29 #define INTEL_CX0_LANE1 BIT(1)
43 hweight8(lane_mask) != 1)) in lane_mask_to_lane()
59 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
343 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
354 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
437 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
443 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1), in intel_cx0_phy_set_signal_levels()
462 intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), in intel_cx0_phy_set_signal_levels()
478 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
496 .pll[1] = 0,
522 .pll[1] = 0,
548 .pll[1] = 0,
574 .pll[1] = 0,
600 .pll[1] = 0,
626 .pll[1] = 0,
652 .pll[1] = 0,
678 .pll[1] = 0,
704 .pll[1] = 0,
849 .clock = 1000000, /* 10 Gbps */
873 .clock = 1350000, /* 13.5 Gbps */
898 .clock = 2000000, /* 20 Gbps */
941 .pll[1] = 0,
967 .pll[1] = 0,
993 .pll[1] = 0,
1019 .pll[1] = 0,
1045 .pll[1] = 0,
1071 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1081 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1091 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1101 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1111 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1121 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1131 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1141 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1151 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1161 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1171 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1181 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1191 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1201 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1211 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1221 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1231 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1241 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1251 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1261 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1271 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1281 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1291 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1301 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1311 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1321 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1331 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1341 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1351 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1361 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1371 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1381 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1391 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1401 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1411 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1421 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1431 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1441 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1451 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1461 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1870 intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), in intel_c10pll_readout_hw_state()
1891 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1899 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1912 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1922 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
1949 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], in intel_c10pll_dump_hw_state()
1979 mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), in intel_c20_compute_hdmi_tmds_pll()
1993 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
1996 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2001 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2118 /* 1. Read current context selection */ in intel_c20pll_readout_hw_state()
2172 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2173 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2174 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2175 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2189 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2191 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2192 return 1; in intel_c20_get_dp_rate()
2193 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2195 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2197 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2199 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2201 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2203 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2205 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2207 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2209 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2211 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2213 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2227 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2228 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2229 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2230 return 1; in intel_c20_get_hdmi_rate()
2231 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2233 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2253 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2254 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2255 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2256 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2257 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2278 return 1; in intel_get_c20_custom_width()
2297 /* 1. Read current context selection */ in intel_c20_pll_program()
2381 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2387 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2406 tmpclk *= (hdmi_div ? 2 : 1); in intel_c10pll_calc_port_clock()
2424 tx_rate_mult = 1; in intel_c20pll_calc_port_clock()
2440 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2450 ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); in intel_c20pll_calc_port_clock()
2589 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2593 XELPDP_LANE_PHY_CURRENT_STATUS(1)) in intel_cx0_phy_lane_reset()
2647 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2656 if (dp_alt_mode && lane_count == 1) { in intel_cx0_program_phy_lane()
2657 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2658 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2662 int tx = i % 2 + 1; in intel_cx0_program_phy_lane()
2676 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2715 * 1. Program PORT_CLOCK_CTL REGISTER to configure in intel_cx0pll_enable()
2762 * LN<Lane for maxPCLK> to "1" to enable PLL. in intel_cx0pll_enable()
2768 /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ in intel_cx0pll_enable()
2837 * 1. Program PORT_CLOCK_CTL REGISTER to configure in intel_mtl_tbt_pll_enable()
2854 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. in intel_mtl_tbt_pll_enable()
2859 /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ in intel_mtl_tbt_pll_enable()
2898 /* 1. Change owned PHY lane power to Disable state. */ in intel_cx0pll_disable()
2949 * 1. Follow the Display Voltage Frequency Switching Sequence Before in intel_mtl_tbt_pll_disable()