Lines Matching +full:0 +full:x23
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
44 return 0; in lane_mask_to_lane()
58 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
121 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
152 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
166 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
173 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
179 return 0; in intel_cx0_wait_for_ack()
204 if (ack < 0) in __intel_cx0_read_once()
228 for (i = 0; i < 3; i++) { in __intel_cx0_read()
231 if (status >= 0) in __intel_cx0_read()
238 return 0; in __intel_cx0_read()
283 if (ack < 0) in __intel_cx0_write_once()
302 return 0; in __intel_cx0_write_once()
314 for (i = 0; i < 3; i++) { in __intel_cx0_write()
317 if (status == 0) in __intel_cx0_write()
339 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
340 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
342 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
343 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
353 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
354 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
438 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
449 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
453 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
458 intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
472 /* Write Override enables in 0xD71 */ in intel_cx0_phy_set_signal_levels()
474 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, in intel_cx0_phy_set_signal_levels()
479 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
487 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
488 * programmed 0.
493 .tx = 0x10,
494 .cmn = 0x21,
495 .pll[0] = 0xB4,
496 .pll[1] = 0,
497 .pll[2] = 0x30,
498 .pll[3] = 0x1,
499 .pll[4] = 0x26,
500 .pll[5] = 0x0C,
501 .pll[6] = 0x98,
502 .pll[7] = 0x46,
503 .pll[8] = 0x1,
504 .pll[9] = 0x1,
505 .pll[10] = 0,
506 .pll[11] = 0,
507 .pll[12] = 0xC0,
508 .pll[13] = 0,
509 .pll[14] = 0,
510 .pll[15] = 0x2,
511 .pll[16] = 0x84,
512 .pll[17] = 0x4F,
513 .pll[18] = 0xE5,
514 .pll[19] = 0x23,
519 .tx = 0x10,
520 .cmn = 0x21,
521 .pll[0] = 0x4,
522 .pll[1] = 0,
523 .pll[2] = 0xA2,
524 .pll[3] = 0x1,
525 .pll[4] = 0x33,
526 .pll[5] = 0x10,
527 .pll[6] = 0x75,
528 .pll[7] = 0xB3,
529 .pll[8] = 0x1,
530 .pll[9] = 0x1,
531 .pll[10] = 0,
532 .pll[11] = 0,
533 .pll[12] = 0,
534 .pll[13] = 0,
535 .pll[14] = 0,
536 .pll[15] = 0x2,
537 .pll[16] = 0x85,
538 .pll[17] = 0x0F,
539 .pll[18] = 0xE6,
540 .pll[19] = 0x23,
545 .tx = 0x10,
546 .cmn = 0x21,
547 .pll[0] = 0x34,
548 .pll[1] = 0,
549 .pll[2] = 0xDA,
550 .pll[3] = 0x1,
551 .pll[4] = 0x39,
552 .pll[5] = 0x12,
553 .pll[6] = 0xE3,
554 .pll[7] = 0xE9,
555 .pll[8] = 0x1,
556 .pll[9] = 0x1,
557 .pll[10] = 0,
558 .pll[11] = 0,
559 .pll[12] = 0x20,
560 .pll[13] = 0,
561 .pll[14] = 0,
562 .pll[15] = 0x2,
563 .pll[16] = 0x85,
564 .pll[17] = 0x8F,
565 .pll[18] = 0xE6,
566 .pll[19] = 0x23,
571 .tx = 0x10,
572 .cmn = 0x21,
573 .pll[0] = 0xF4,
574 .pll[1] = 0,
575 .pll[2] = 0xF8,
576 .pll[3] = 0x0,
577 .pll[4] = 0x20,
578 .pll[5] = 0x0A,
579 .pll[6] = 0x29,
580 .pll[7] = 0x10,
581 .pll[8] = 0x1, /* Verify */
582 .pll[9] = 0x1,
583 .pll[10] = 0,
584 .pll[11] = 0,
585 .pll[12] = 0xA0,
586 .pll[13] = 0,
587 .pll[14] = 0,
588 .pll[15] = 0x1,
589 .pll[16] = 0x84,
590 .pll[17] = 0x4F,
591 .pll[18] = 0xE5,
592 .pll[19] = 0x23,
597 .tx = 0x10,
598 .cmn = 0x21,
599 .pll[0] = 0xB4,
600 .pll[1] = 0,
601 .pll[2] = 0x30,
602 .pll[3] = 0x1,
603 .pll[4] = 0x26,
604 .pll[5] = 0x0C,
605 .pll[6] = 0x98,
606 .pll[7] = 0x46,
607 .pll[8] = 0x1,
608 .pll[9] = 0x1,
609 .pll[10] = 0,
610 .pll[11] = 0,
611 .pll[12] = 0xC0,
612 .pll[13] = 0,
613 .pll[14] = 0,
614 .pll[15] = 0x1,
615 .pll[16] = 0x85,
616 .pll[17] = 0x4F,
617 .pll[18] = 0xE6,
618 .pll[19] = 0x23,
623 .tx = 0x10,
624 .cmn = 0x21,
625 .pll[0] = 0x4,
626 .pll[1] = 0,
627 .pll[2] = 0xA2,
628 .pll[3] = 0x1,
629 .pll[4] = 0x33,
630 .pll[5] = 0x10,
631 .pll[6] = 0x75,
632 .pll[7] = 0xB3,
633 .pll[8] = 0x1,
634 .pll[9] = 0x1,
635 .pll[10] = 0,
636 .pll[11] = 0,
637 .pll[12] = 0,
638 .pll[13] = 0,
639 .pll[14] = 0,
640 .pll[15] = 0x1,
641 .pll[16] = 0x85,
642 .pll[17] = 0x0F,
643 .pll[18] = 0xE6,
644 .pll[19] = 0x23,
649 .tx = 0x10,
650 .cmn = 0x21,
651 .pll[0] = 0xF4,
652 .pll[1] = 0,
653 .pll[2] = 0xF8,
654 .pll[3] = 0,
655 .pll[4] = 0x20,
656 .pll[5] = 0x0A,
657 .pll[6] = 0x29,
658 .pll[7] = 0x10,
659 .pll[8] = 0x1,
660 .pll[9] = 0x1,
661 .pll[10] = 0,
662 .pll[11] = 0,
663 .pll[12] = 0xA0,
664 .pll[13] = 0,
665 .pll[14] = 0,
666 .pll[15] = 0,
667 .pll[16] = 0x84,
668 .pll[17] = 0x4F,
669 .pll[18] = 0xE5,
670 .pll[19] = 0x23,
675 .tx = 0x10,
676 .cmn = 0x21,
677 .pll[0] = 0xB4,
678 .pll[1] = 0,
679 .pll[2] = 0x3E,
680 .pll[3] = 0x1,
681 .pll[4] = 0xA8,
682 .pll[5] = 0x0C,
683 .pll[6] = 0x33,
684 .pll[7] = 0x54,
685 .pll[8] = 0x1,
686 .pll[9] = 0x1,
687 .pll[10] = 0,
688 .pll[11] = 0,
689 .pll[12] = 0xC8,
690 .pll[13] = 0,
691 .pll[14] = 0,
692 .pll[15] = 0,
693 .pll[16] = 0x85,
694 .pll[17] = 0x8F,
695 .pll[18] = 0xE6,
696 .pll[19] = 0x23,
701 .tx = 0x10,
702 .cmn = 0x21,
703 .pll[0] = 0x34,
704 .pll[1] = 0,
705 .pll[2] = 0x84,
706 .pll[3] = 0x1,
707 .pll[4] = 0x30,
708 .pll[5] = 0x0F,
709 .pll[6] = 0x3D,
710 .pll[7] = 0x98,
711 .pll[8] = 0x1,
712 .pll[9] = 0x1,
713 .pll[10] = 0,
714 .pll[11] = 0,
715 .pll[12] = 0xF0,
716 .pll[13] = 0,
717 .pll[14] = 0,
718 .pll[15] = 0,
719 .pll[16] = 0x84,
720 .pll[17] = 0x0F,
721 .pll[18] = 0xE5,
722 .pll[19] = 0x23,
749 .tx = { 0xbe88, /* tx cfg0 */
750 0x5800, /* tx cfg1 */
751 0x0000, /* tx cfg2 */
753 .cmn = {0x0500, /* cmn cfg0*/
754 0x0005, /* cmn cfg1 */
755 0x0000, /* cmn cfg2 */
756 0x0000, /* cmn cfg3 */
758 .mpllb = { 0x50a8, /* mpllb cfg0 */
759 0x2120, /* mpllb cfg1 */
760 0xcd9a, /* mpllb cfg2 */
761 0xbfc1, /* mpllb cfg3 */
762 0x5ab8, /* mpllb cfg4 */
763 0x4c34, /* mpllb cfg5 */
764 0x2000, /* mpllb cfg6 */
765 0x0001, /* mpllb cfg7 */
766 0x6000, /* mpllb cfg8 */
767 0x0000, /* mpllb cfg9 */
768 0x0000, /* mpllb cfg10 */
774 .tx = { 0xbe88, /* tx cfg0 */
775 0x4800, /* tx cfg1 */
776 0x0000, /* tx cfg2 */
778 .cmn = {0x0500, /* cmn cfg0*/
779 0x0005, /* cmn cfg1 */
780 0x0000, /* cmn cfg2 */
781 0x0000, /* cmn cfg3 */
783 .mpllb = { 0x308c, /* mpllb cfg0 */
784 0x2110, /* mpllb cfg1 */
785 0xcc9c, /* mpllb cfg2 */
786 0xbfc1, /* mpllb cfg3 */
787 0x4b9a, /* mpllb cfg4 */
788 0x3f81, /* mpllb cfg5 */
789 0x2000, /* mpllb cfg6 */
790 0x0001, /* mpllb cfg7 */
791 0x5000, /* mpllb cfg8 */
792 0x0000, /* mpllb cfg9 */
793 0x0000, /* mpllb cfg10 */
799 .tx = { 0xbe88, /* tx cfg0 */
800 0x4800, /* tx cfg1 */
801 0x0000, /* tx cfg2 */
803 .cmn = {0x0500, /* cmn cfg0*/
804 0x0005, /* cmn cfg1 */
805 0x0000, /* cmn cfg2 */
806 0x0000, /* cmn cfg3 */
808 .mpllb = { 0x108c, /* mpllb cfg0 */
809 0x2108, /* mpllb cfg1 */
810 0xcc9c, /* mpllb cfg2 */
811 0xbfc1, /* mpllb cfg3 */
812 0x4b9a, /* mpllb cfg4 */
813 0x3f81, /* mpllb cfg5 */
814 0x2000, /* mpllb cfg6 */
815 0x0001, /* mpllb cfg7 */
816 0x5000, /* mpllb cfg8 */
817 0x0000, /* mpllb cfg9 */
818 0x0000, /* mpllb cfg10 */
824 .tx = { 0xbe88, /* tx cfg0 */
825 0x4800, /* tx cfg1 */
826 0x0000, /* tx cfg2 */
828 .cmn = {0x0500, /* cmn cfg0*/
829 0x0005, /* cmn cfg1 */
830 0x0000, /* cmn cfg2 */
831 0x0000, /* cmn cfg3 */
833 .mpllb = { 0x10d2, /* mpllb cfg0 */
834 0x2108, /* mpllb cfg1 */
835 0x8d98, /* mpllb cfg2 */
836 0xbfc1, /* mpllb cfg3 */
837 0x7166, /* mpllb cfg4 */
838 0x5f42, /* mpllb cfg5 */
839 0x2000, /* mpllb cfg6 */
840 0x0001, /* mpllb cfg7 */
841 0x7800, /* mpllb cfg8 */
842 0x0000, /* mpllb cfg9 */
843 0x0000, /* mpllb cfg10 */
850 .tx = { 0xbe21, /* tx cfg0 */
851 0x4800, /* tx cfg1 */
852 0x0000, /* tx cfg2 */
854 .cmn = {0x0500, /* cmn cfg0*/
855 0x0005, /* cmn cfg1 */
856 0x0000, /* cmn cfg2 */
857 0x0000, /* cmn cfg3 */
859 .mplla = { 0x3104, /* mplla cfg0 */
860 0xd105, /* mplla cfg1 */
861 0xc025, /* mplla cfg2 */
862 0xc025, /* mplla cfg3 */
863 0x8c00, /* mplla cfg4 */
864 0x759a, /* mplla cfg5 */
865 0x4000, /* mplla cfg6 */
866 0x0003, /* mplla cfg7 */
867 0x3555, /* mplla cfg8 */
868 0x0001, /* mplla cfg9 */
874 .tx = { 0xbea0, /* tx cfg0 */
875 0x4800, /* tx cfg1 */
876 0x0000, /* tx cfg2 */
878 .cmn = {0x0500, /* cmn cfg0*/
879 0x0005, /* cmn cfg1 */
880 0x0000, /* cmn cfg2 */
881 0x0000, /* cmn cfg3 */
883 .mpllb = { 0x015f, /* mpllb cfg0 */
884 0x2205, /* mpllb cfg1 */
885 0x1b17, /* mpllb cfg2 */
886 0xffc1, /* mpllb cfg3 */
887 0xe100, /* mpllb cfg4 */
888 0xbd00, /* mpllb cfg5 */
889 0x2000, /* mpllb cfg6 */
890 0x0001, /* mpllb cfg7 */
891 0x4800, /* mpllb cfg8 */
892 0x0000, /* mpllb cfg9 */
893 0x0000, /* mpllb cfg10 */
899 .tx = { 0xbe20, /* tx cfg0 */
900 0x4800, /* tx cfg1 */
901 0x0000, /* tx cfg2 */
903 .cmn = {0x0500, /* cmn cfg0*/
904 0x0005, /* cmn cfg1 */
905 0x0000, /* cmn cfg2 */
906 0x0000, /* cmn cfg3 */
908 .mplla = { 0x3104, /* mplla cfg0 */
909 0xd105, /* mplla cfg1 */
910 0xc025, /* mplla cfg2 */
911 0xc025, /* mplla cfg3 */
912 0xa6ab, /* mplla cfg4 */
913 0x8c00, /* mplla cfg5 */
914 0x4000, /* mplla cfg6 */
915 0x0003, /* mplla cfg7 */
916 0x3555, /* mplla cfg8 */
917 0x0001, /* mplla cfg9 */
938 .tx = 0x10,
939 .cmn = 0x1,
940 .pll[0] = 0x4,
941 .pll[1] = 0,
942 .pll[2] = 0xB2,
943 .pll[3] = 0,
944 .pll[4] = 0,
945 .pll[5] = 0,
946 .pll[6] = 0,
947 .pll[7] = 0,
948 .pll[8] = 0x20,
949 .pll[9] = 0x1,
950 .pll[10] = 0,
951 .pll[11] = 0,
952 .pll[12] = 0,
953 .pll[13] = 0,
954 .pll[14] = 0,
955 .pll[15] = 0xD,
956 .pll[16] = 0x6,
957 .pll[17] = 0x8F,
958 .pll[18] = 0x84,
959 .pll[19] = 0x23,
964 .tx = 0x10,
965 .cmn = 0x1,
966 .pll[0] = 0x34,
967 .pll[1] = 0,
968 .pll[2] = 0xC0,
969 .pll[3] = 0,
970 .pll[4] = 0,
971 .pll[5] = 0,
972 .pll[6] = 0,
973 .pll[7] = 0,
974 .pll[8] = 0x20,
975 .pll[9] = 0x1,
976 .pll[10] = 0,
977 .pll[11] = 0,
978 .pll[12] = 0x80,
979 .pll[13] = 0,
980 .pll[14] = 0,
981 .pll[15] = 0xD,
982 .pll[16] = 0x6,
983 .pll[17] = 0xCF,
984 .pll[18] = 0x84,
985 .pll[19] = 0x23,
990 .tx = 0x10,
991 .cmn = 0x1,
992 .pll[0] = 0xF4,
993 .pll[1] = 0,
994 .pll[2] = 0x7A,
995 .pll[3] = 0,
996 .pll[4] = 0,
997 .pll[5] = 0,
998 .pll[6] = 0,
999 .pll[7] = 0,
1000 .pll[8] = 0x20,
1001 .pll[9] = 0x1,
1002 .pll[10] = 0,
1003 .pll[11] = 0,
1004 .pll[12] = 0x58,
1005 .pll[13] = 0,
1006 .pll[14] = 0,
1007 .pll[15] = 0xB,
1008 .pll[16] = 0x6,
1009 .pll[17] = 0xF,
1010 .pll[18] = 0x85,
1011 .pll[19] = 0x23,
1016 .tx = 0x10,
1017 .cmn = 0x1,
1018 .pll[0] = 0xF4,
1019 .pll[1] = 0,
1020 .pll[2] = 0x7A,
1021 .pll[3] = 0,
1022 .pll[4] = 0,
1023 .pll[5] = 0,
1024 .pll[6] = 0,
1025 .pll[7] = 0,
1026 .pll[8] = 0x20,
1027 .pll[9] = 0x1,
1028 .pll[10] = 0,
1029 .pll[11] = 0,
1030 .pll[12] = 0x58,
1031 .pll[13] = 0,
1032 .pll[14] = 0,
1033 .pll[15] = 0xA,
1034 .pll[16] = 0x6,
1035 .pll[17] = 0xF,
1036 .pll[18] = 0x85,
1037 .pll[19] = 0x23,
1042 .tx = 0x10,
1043 .cmn = 0x1,
1044 .pll[0] = 0xF4,
1045 .pll[1] = 0,
1046 .pll[2] = 0x7A,
1047 .pll[3] = 0,
1048 .pll[4] = 0,
1049 .pll[5] = 0,
1050 .pll[6] = 0,
1051 .pll[7] = 0,
1052 .pll[8] = 0x20,
1053 .pll[9] = 0x1,
1054 .pll[10] = 0,
1055 .pll[11] = 0,
1056 .pll[12] = 0x58,
1057 .pll[13] = 0,
1058 .pll[14] = 0,
1059 .pll[15] = 0x8,
1060 .pll[16] = 0x6,
1061 .pll[17] = 0xF,
1062 .pll[18] = 0x85,
1063 .pll[19] = 0x23,
1069 .tx = 0x10,
1070 .cmn = 0x1,
1071 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1072 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1073 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
1074 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1079 .tx = 0x10,
1080 .cmn = 0x1,
1081 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1082 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1083 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1084 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1089 .tx = 0x10,
1090 .cmn = 0x1,
1091 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1092 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1093 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1094 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1099 .tx = 0x10,
1100 .cmn = 0x1,
1101 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1102 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1103 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
1104 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1109 .tx = 0x10,
1110 .cmn = 0x1,
1111 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1112 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1113 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1114 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1119 .tx = 0x10,
1120 .cmn = 0x1,
1121 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1122 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1123 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
1124 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1129 .tx = 0x10,
1130 .cmn = 0x1,
1131 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1132 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1133 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1134 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1139 .tx = 0x10,
1140 .cmn = 0x1,
1141 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1142 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1143 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
1144 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1149 .tx = 0x10,
1150 .cmn = 0x1,
1151 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1152 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1153 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
1154 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1159 .tx = 0x10,
1160 .cmn = 0x1,
1161 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1162 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1163 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
1164 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1169 .tx = 0x10,
1170 .cmn = 0x1,
1171 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1172 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1173 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
1174 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1179 .tx = 0x10,
1180 .cmn = 0x1,
1181 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1182 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1183 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1184 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1189 .tx = 0x10,
1190 .cmn = 0x1,
1191 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1192 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1193 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1194 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1199 .tx = 0x10,
1200 .cmn = 0x1,
1201 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1202 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1203 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1204 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1209 .tx = 0x10,
1210 .cmn = 0x1,
1211 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1212 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1213 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
1214 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1219 .tx = 0x10,
1220 .cmn = 0x1,
1221 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1222 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1223 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
1224 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1229 .tx = 0x10,
1230 .cmn = 0x1,
1231 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1232 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1233 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
1234 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1239 .tx = 0x10,
1240 .cmn = 0x1,
1241 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1242 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1243 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
1244 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1249 .tx = 0x10,
1250 .cmn = 0x1,
1251 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1252 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1253 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
1254 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1259 .tx = 0x10,
1260 .cmn = 0x1,
1261 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1262 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1263 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1264 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1269 .tx = 0x10,
1270 .cmn = 0x1,
1271 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1272 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1273 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1274 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1279 .tx = 0x10,
1280 .cmn = 0x1,
1281 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1282 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1283 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1284 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1289 .tx = 0x10,
1290 .cmn = 0x1,
1291 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1292 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1293 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
1294 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1299 .tx = 0x10,
1300 .cmn = 0x1,
1301 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1302 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1303 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
1304 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1309 .tx = 0x10,
1310 .cmn = 0x1,
1311 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1312 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1313 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1314 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1319 .tx = 0x10,
1320 .cmn = 0x1,
1321 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1322 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1323 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
1324 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1329 .tx = 0x10,
1330 .cmn = 0x1,
1331 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1332 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1333 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
1334 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1339 .tx = 0x10,
1340 .cmn = 0x1,
1341 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1342 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1343 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
1344 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1349 .tx = 0x10,
1350 .cmn = 0x1,
1351 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1352 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1353 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
1354 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1359 .tx = 0x10,
1360 .cmn = 0x1,
1361 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1362 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1363 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1364 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1369 .tx = 0x10,
1370 .cmn = 0x1,
1371 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1372 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1373 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
1374 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1379 .tx = 0x10,
1380 .cmn = 0x1,
1381 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1382 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1383 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
1384 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1389 .tx = 0x10,
1390 .cmn = 0x1,
1391 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1392 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1393 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
1394 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1399 .tx = 0x10,
1400 .cmn = 0x1,
1401 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1402 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1403 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
1404 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1409 .tx = 0x10,
1410 .cmn = 0x1,
1411 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1412 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1413 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
1414 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1419 .tx = 0x10,
1420 .cmn = 0x1,
1421 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1422 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1423 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
1424 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1429 .tx = 0x10,
1430 .cmn = 0x1,
1431 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1432 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1433 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
1434 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1439 .tx = 0x10,
1440 .cmn = 0x1,
1441 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1442 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1443 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
1444 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1449 .tx = 0x10,
1450 .cmn = 0x1,
1451 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1452 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1453 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
1454 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1459 .tx = 0x10,
1460 .cmn = 0x1,
1461 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1462 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1463 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
1464 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1518 .tx = { 0xbe88, /* tx cfg0 */
1519 0x9800, /* tx cfg1 */
1520 0x0000, /* tx cfg2 */
1522 .cmn = { 0x0500, /* cmn cfg0*/
1523 0x0005, /* cmn cfg1 */
1524 0x0000, /* cmn cfg2 */
1525 0x0000, /* cmn cfg3 */
1527 .mpllb = { 0xa0d2, /* mpllb cfg0 */
1528 0x7d80, /* mpllb cfg1 */
1529 0x0906, /* mpllb cfg2 */
1530 0xbe40, /* mpllb cfg3 */
1531 0x0000, /* mpllb cfg4 */
1532 0x0000, /* mpllb cfg5 */
1533 0x0200, /* mpllb cfg6 */
1534 0x0001, /* mpllb cfg7 */
1535 0x0000, /* mpllb cfg8 */
1536 0x0000, /* mpllb cfg9 */
1537 0x0001, /* mpllb cfg10 */
1543 .tx = { 0xbe88, /* tx cfg0 */
1544 0x9800, /* tx cfg1 */
1545 0x0000, /* tx cfg2 */
1547 .cmn = { 0x0500, /* cmn cfg0*/
1548 0x0005, /* cmn cfg1 */
1549 0x0000, /* cmn cfg2 */
1550 0x0000, /* cmn cfg3 */
1552 .mpllb = { 0xa0e0, /* mpllb cfg0 */
1553 0x7d80, /* mpllb cfg1 */
1554 0x0906, /* mpllb cfg2 */
1555 0xbe40, /* mpllb cfg3 */
1556 0x0000, /* mpllb cfg4 */
1557 0x0000, /* mpllb cfg5 */
1558 0x2200, /* mpllb cfg6 */
1559 0x0001, /* mpllb cfg7 */
1560 0x8000, /* mpllb cfg8 */
1561 0x0000, /* mpllb cfg9 */
1562 0x0001, /* mpllb cfg10 */
1568 .tx = { 0xbe88, /* tx cfg0 */
1569 0x9800, /* tx cfg1 */
1570 0x0000, /* tx cfg2 */
1572 .cmn = { 0x0500, /* cmn cfg0*/
1573 0x0005, /* cmn cfg1 */
1574 0x0000, /* cmn cfg2 */
1575 0x0000, /* cmn cfg3 */
1577 .mpllb = { 0x609a, /* mpllb cfg0 */
1578 0x7d40, /* mpllb cfg1 */
1579 0xca06, /* mpllb cfg2 */
1580 0xbe40, /* mpllb cfg3 */
1581 0x0000, /* mpllb cfg4 */
1582 0x0000, /* mpllb cfg5 */
1583 0x2200, /* mpllb cfg6 */
1584 0x0001, /* mpllb cfg7 */
1585 0x5800, /* mpllb cfg8 */
1586 0x0000, /* mpllb cfg9 */
1587 0x0001, /* mpllb cfg10 */
1593 .tx = { 0xbe88, /* tx cfg0 */
1594 0x9800, /* tx cfg1 */
1595 0x0000, /* tx cfg2 */
1597 .cmn = { 0x0500, /* cmn cfg0*/
1598 0x0005, /* cmn cfg1 */
1599 0x0000, /* cmn cfg2 */
1600 0x0000, /* cmn cfg3 */
1602 .mpllb = { 0x409a, /* mpllb cfg0 */
1603 0x7d20, /* mpllb cfg1 */
1604 0xca06, /* mpllb cfg2 */
1605 0xbe40, /* mpllb cfg3 */
1606 0x0000, /* mpllb cfg4 */
1607 0x0000, /* mpllb cfg5 */
1608 0x2200, /* mpllb cfg6 */
1609 0x0001, /* mpllb cfg7 */
1610 0x5800, /* mpllb cfg8 */
1611 0x0000, /* mpllb cfg9 */
1612 0x0001, /* mpllb cfg10 */
1618 .tx = { 0xbe88, /* tx cfg0 */
1619 0x9800, /* tx cfg1 */
1620 0x0000, /* tx cfg2 */
1622 .cmn = { 0x0500, /* cmn cfg0*/
1623 0x0005, /* cmn cfg1 */
1624 0x0000, /* cmn cfg2 */
1625 0x0000, /* cmn cfg3 */
1627 .mpllb = { 0x009a, /* mpllb cfg0 */
1628 0x7d08, /* mpllb cfg1 */
1629 0xca06, /* mpllb cfg2 */
1630 0xbe40, /* mpllb cfg3 */
1631 0x0000, /* mpllb cfg4 */
1632 0x0000, /* mpllb cfg5 */
1633 0x2200, /* mpllb cfg6 */
1634 0x0001, /* mpllb cfg7 */
1635 0x5800, /* mpllb cfg8 */
1636 0x0000, /* mpllb cfg9 */
1637 0x0001, /* mpllb cfg10 */
1643 .tx = { 0xbe98, /* tx cfg0 */
1644 0x9800, /* tx cfg1 */
1645 0x0000, /* tx cfg2 */
1647 .cmn = { 0x0500, /* cmn cfg0*/
1648 0x0005, /* cmn cfg1 */
1649 0x0000, /* cmn cfg2 */
1650 0x0000, /* cmn cfg3 */
1652 .mpllb = { 0x209c, /* mpllb cfg0 */
1653 0x7d10, /* mpllb cfg1 */
1654 0xca06, /* mpllb cfg2 */
1655 0xbe40, /* mpllb cfg3 */
1656 0x0000, /* mpllb cfg4 */
1657 0x0000, /* mpllb cfg5 */
1658 0x2200, /* mpllb cfg6 */
1659 0x0001, /* mpllb cfg7 */
1660 0x2000, /* mpllb cfg8 */
1661 0x0000, /* mpllb cfg9 */
1662 0x0004, /* mpllb cfg10 */
1668 .tx = { 0xbe98, /* tx cfg0 */
1669 0x9800, /* tx cfg1 */
1670 0x0000, /* tx cfg2 */
1672 .cmn = { 0x0500, /* cmn cfg0*/
1673 0x0005, /* cmn cfg1 */
1674 0x0000, /* cmn cfg2 */
1675 0x0000, /* cmn cfg3 */
1677 .mpllb = { 0x009c, /* mpllb cfg0 */
1678 0x7d08, /* mpllb cfg1 */
1679 0xca06, /* mpllb cfg2 */
1680 0xbe40, /* mpllb cfg3 */
1681 0x0000, /* mpllb cfg4 */
1682 0x0000, /* mpllb cfg5 */
1683 0x2200, /* mpllb cfg6 */
1684 0x0001, /* mpllb cfg7 */
1685 0x2000, /* mpllb cfg8 */
1686 0x0000, /* mpllb cfg9 */
1687 0x0004, /* mpllb cfg10 */
1693 .tx = { 0xbe98, /* tx cfg0 */
1694 0x9800, /* tx cfg1 */
1695 0x0000, /* tx cfg2 */
1697 .cmn = { 0x0500, /* cmn cfg0*/
1698 0x0005, /* cmn cfg1 */
1699 0x0000, /* cmn cfg2 */
1700 0x0000, /* cmn cfg3 */
1702 .mpllb = { 0x00d0, /* mpllb cfg0 */
1703 0x7d08, /* mpllb cfg1 */
1704 0x4a06, /* mpllb cfg2 */
1705 0xbe40, /* mpllb cfg3 */
1706 0x0000, /* mpllb cfg4 */
1707 0x0000, /* mpllb cfg5 */
1708 0x2200, /* mpllb cfg6 */
1709 0x0003, /* mpllb cfg7 */
1710 0x2aaa, /* mpllb cfg8 */
1711 0x0002, /* mpllb cfg9 */
1712 0x0004, /* mpllb cfg10 */
1718 .tx = { 0xbe98, /* tx cfg0 */
1719 0x9800, /* tx cfg1 */
1720 0x0000, /* tx cfg2 */
1722 .cmn = { 0x0500, /* cmn cfg0*/
1723 0x0005, /* cmn cfg1 */
1724 0x0000, /* cmn cfg2 */
1725 0x0000, /* cmn cfg3 */
1727 .mpllb = { 0x1104, /* mpllb cfg0 */
1728 0x7d08, /* mpllb cfg1 */
1729 0x0a06, /* mpllb cfg2 */
1730 0xbe40, /* mpllb cfg3 */
1731 0x0000, /* mpllb cfg4 */
1732 0x0000, /* mpllb cfg5 */
1733 0x2200, /* mpllb cfg6 */
1734 0x0003, /* mpllb cfg7 */
1735 0x3555, /* mpllb cfg8 */
1736 0x0001, /* mpllb cfg9 */
1737 0x0004, /* mpllb cfg10 */
1743 .tx = { 0xbe98, /* tx cfg0 */
1744 0x9800, /* tx cfg1 */
1745 0x0000, /* tx cfg2 */
1747 .cmn = { 0x0500, /* cmn cfg0*/
1748 0x0005, /* cmn cfg1 */
1749 0x0000, /* cmn cfg2 */
1750 0x0000, /* cmn cfg3 */
1752 .mpllb = { 0x0138, /* mpllb cfg0 */
1753 0x7d08, /* mpllb cfg1 */
1754 0x5486, /* mpllb cfg2 */
1755 0xfe40, /* mpllb cfg3 */
1756 0x0000, /* mpllb cfg4 */
1757 0x0000, /* mpllb cfg5 */
1758 0x2200, /* mpllb cfg6 */
1759 0x0001, /* mpllb cfg7 */
1760 0x4000, /* mpllb cfg8 */
1761 0x0000, /* mpllb cfg9 */
1762 0x0004, /* mpllb cfg10 */
1785 for (i = 0; tables[i]; i++) { in intel_c10_phy_check_hdmi_link_rate()
1831 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
1844 for (i = 0; tables[i]; i++) { in intel_c10pll_calc_state()
1849 return 0; in intel_c10pll_calc_state()
1871 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10pll_readout_hw_state()
1874 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
1878 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
1879 pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
1892 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10_pll_program()
1895 /* Custom width needs to be programmed to 0 for both the phy lanes */ in intel_c10_pll_program()
1900 0, C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
1904 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
1909 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE… in intel_c10_pll_program()
1910 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_C… in intel_c10_pll_program()
1913 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
1922 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
1925 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
1944 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); in intel_c10pll_dump_hw_state()
1947 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
1948 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
1976 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
1977 mpll_fracn_rem = multiplier & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
1992 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
1993 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
1994 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1995 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
1996 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
1997 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1998 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1999 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2010 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2011 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2018 return 0; in intel_c20_compute_hdmi_tmds_pll()
2026 for (i = 0; tables[i]; i++) { in intel_c20_phy_check_hdmi_link_rate()
2070 &crtc_state->cx0pll_state.c20) == 0) in intel_c20pll_calc_state()
2071 return 0; in intel_c20pll_calc_state()
2078 for (i = 0; tables[i]; i++) { in intel_c20pll_calc_state()
2081 return 0; in intel_c20pll_calc_state()
2122 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2132 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2141 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_readout_hw_state()
2143 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2153 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2172 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2173 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2174 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2175 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2178 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2179 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); in intel_c20pll_dump_hw_state()
2181 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2182 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
2190 return 0; in intel_c20_get_dp_rate()
2205 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2207 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2209 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2217 return 0; in intel_c20_get_dp_rate()
2224 return 0; in intel_c20_get_hdmi_rate()
2237 return 0; in intel_c20_get_hdmi_rate()
2243 /* DP2.0 clock rates */ in is_dp2()
2280 return 0; in intel_get_c20_custom_width()
2298 …tx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); in intel_c20_pll_program()
2302 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2306 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2307 …c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); in intel_c20_pll_program()
2313 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2321 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2330 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2341 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2368 is_hdmi_frl(clock) ? BIT(7) : 0, in intel_c20_pll_program()
2381 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2387 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2389 int tmpclk = 0; in intel_c10pll_calc_port_clock()
2391 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2421 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2423 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_calc_port_clock()
2429 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2430 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2432 fb_clk_div4_en = 0; in intel_c20pll_calc_port_clock()
2439 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2442 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2448 frac = 0; in intel_c20pll_calc_port_clock()
2461 u32 val = 0; in intel_program_port_clock_ctl()
2464 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()
2478 /* DP2.0 10G and 20G rates enable MPLLA*/ in intel_program_port_clock_ctl()
2480 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2482 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2492 u32 val = 0; in intel_cx0_get_powerdown_update()
2493 int lane = 0; in intel_cx0_get_powerdown_update()
2503 u32 val = 0; in intel_cx0_get_powerdown_state()
2504 int lane = 0; in intel_cx0_get_powerdown_state()
2540 intel_cx0_get_powerdown_update(lane_mask), 0, in intel_cx0_powerdown_change_sequence()
2541 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) in intel_cx0_powerdown_change_sequence()
2555 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); in intel_cx0_setup_powerdown()
2560 u32 val = 0; in intel_cx0_get_pclk_refclk_request()
2561 int lane = 0; in intel_cx0_get_pclk_refclk_request()
2571 u32 val = 0; in intel_cx0_get_pclk_refclk_ack()
2572 int lane = 0; in intel_cx0_get_pclk_refclk_ack()
2589 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2590 : XELPDP_LANE_PIPE_RESET(0); in intel_cx0_phy_lane_reset()
2592 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | in intel_cx0_phy_lane_reset()
2594 : XELPDP_LANE_PHY_CURRENT_STATUS(0); in intel_cx0_phy_lane_reset()
2599 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2608 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2619 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2627 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2647 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2652 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2654 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2657 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2658 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2661 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
2670 disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, in intel_cx0_program_phy_lane()
2676 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2683 u32 val = 0; in intel_cx0_get_pclk_pll_request()
2684 int lane = 0; in intel_cx0_get_pclk_pll_request()
2694 u32 val = 0; in intel_cx0_get_pclk_pll_ack()
2695 int lane = 0; in intel_cx0_get_pclk_pll_ack()
2731 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in intel_cx0pll_enable()
2772 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_enable()
2834 u32 val = 0; in intel_mtl_tbt_pll_enable()
2863 100, 0, NULL)) in intel_mtl_tbt_pll_enable()
2910 * to "0" to disable PLL. in intel_cx0pll_disable()
2914 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); in intel_cx0pll_disable()
2916 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
2917 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
2920 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
2924 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, in intel_cx0pll_disable()
2925 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_disable()
2936 XELPDP_DDI_CLOCK_SELECT_MASK, 0); in intel_cx0pll_disable()
2938 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_cx0pll_disable()
2954 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()
2957 XELPDP_TBT_CLOCK_REQUEST, 0); in intel_mtl_tbt_pll_disable()
2959 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()
2961 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) in intel_mtl_tbt_pll_disable()
2975 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_mtl_tbt_pll_disable()
2977 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()
2978 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3019 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3023 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3029 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3034 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3070 bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20pll_state_verify()
3071 bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20pll_state_verify()
3080 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3082 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3087 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3089 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3095 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3097 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3102 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3104 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()