42 			    "[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n",  in assert_vblank_disabled()
82 	struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];  in intel_crtc_get_vblank_counter()  local
87 	if (!vblank->max_vblank_count)  in intel_crtc_get_vblank_counter()
135 	 * requires vblank support on some platforms/outputs.  in intel_crtc_vblank_on()
147 	 * requires vblank support on some platforms/outputs.  in intel_crtc_vblank_off()
293 	/* no hw vblank counter */
431 	 * Interrupt latency is critical for getting the vblank  in intel_crtc_vblank_work_init()
432 	 * work executed as early as possible during the vblank.  in intel_crtc_vblank_work_init()
518 	 * undelayed vblank, so with seamless M/N and LRR we must evade  in intel_crtc_vblank_evade_scanlines()
521 	 * DSB execution waits for the transcoder's undelayed vblank,  in intel_crtc_vblank_evade_scanlines()
534  * atomically regarding vblank. If the next vblank will happens within
535  * the next 100 us, this function waits until the vblank passes.
621 	 * increment approx. 1/3 of a scanline before start of vblank.  in intel_pipe_update_start()
622 	 * The registers still get latched at start of vblank however.  in intel_pipe_update_start()
624 	 * line of vblank (since not the whole line is actually in  in intel_pipe_update_start()
625 	 * vblank). And unfortunately we can't use the interrupt to  in intel_pipe_update_start()
685  * before a vblank.
711 	/* We're still in the vblank-evade critical section, this can't race.  in intel_pipe_update_end()
712 	 * Would be slightly nice to just grab the vblank count and arm the  in intel_pipe_update_end()
732 	 * Send VRR Push to terminate Vblank. If we are already in vblank  in intel_pipe_update_end()
734 	 * otherwise the push would immediately terminate the vblank and  in intel_pipe_update_end()
738 	 * There is a tiny race here (iff vblank evasion failed us) where  in intel_pipe_update_end()
739 	 * we might sample the frame counter just before vmax vblank start  in intel_pipe_update_end()
743 	 * vblank start instead of vmax vblank start.  in intel_pipe_update_end()