Lines Matching full:vbl
577 * Wait for psr to idle out after enabling the VBL interrupts in intel_pipe_update_start()
578 * VBL interrupts will start the PSR exit and prevent a PSR in intel_pipe_update_start()
655 if (h >= ARRAY_SIZE(crtc->debug.vbl.times)) in dbg_vblank_evade()
656 h = ARRAY_SIZE(crtc->debug.vbl.times) - 1; in dbg_vblank_evade()
657 crtc->debug.vbl.times[h]++; in dbg_vblank_evade()
659 crtc->debug.vbl.sum += delta; in dbg_vblank_evade()
660 if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min) in dbg_vblank_evade()
661 crtc->debug.vbl.min = delta; in dbg_vblank_evade()
662 if (delta > crtc->debug.vbl.max) in dbg_vblank_evade()
663 crtc->debug.vbl.max = delta; in dbg_vblank_evade()
671 crtc->debug.vbl.over++; in dbg_vblank_evade()