Lines Matching full:phy
55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
99 "Combo PHY %c reg %08x state mismatch: " in check_phy_reg()
101 phy_name(phy), in check_phy_reg()
110 enum phy phy) in icl_verify_procmon_ref_values() argument
115 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_verify_procmon_ref_values()
117 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in icl_verify_procmon_ref_values()
119 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in icl_verify_procmon_ref_values()
121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in icl_verify_procmon_ref_values()
127 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
130 * Some platforms only expect PHY_MISC to be programmed for PHY-A and in has_phy_misc()
131 * PHY-B and may not even have instances of the register for the in has_phy_misc()
132 * other combo PHY's. in has_phy_misc()
135 * that we program it for PHY A. in has_phy_misc()
139 return phy == PHY_A; in has_phy_misc()
143 return phy < PHY_C; in has_phy_misc()
149 enum phy phy) in icl_combo_phy_enabled() argument
151 /* The PHY C added by EHL has no PHY_MISC register */ in icl_combo_phy_enabled()
152 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
153 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
155 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
157 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
168 * the PHY. So if combo PHY A is wired up to drive an external in ehl_vbt_ddi_d_present()
182 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); in ehl_vbt_ddi_d_present()
187 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
202 * We must set the IREFGEN bit for any PHY acting as a master in phy_is_master()
203 * to another PHY. in phy_is_master()
205 if (phy == PHY_A) in phy_is_master()
208 return phy == PHY_D; in phy_is_master()
210 return phy == PHY_C; in phy_is_master()
216 enum phy phy) in icl_combo_phy_verify_state() argument
221 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
225 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), in icl_combo_phy_verify_state()
231 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), in icl_combo_phy_verify_state()
235 ret &= icl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
237 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
238 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
245 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
251 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
258 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
302 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
308 enum phy phy; in icl_combo_phys_init() local
310 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
314 if (icl_combo_phy_verify_state(dev_priv, phy)) in icl_combo_phys_init()
317 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
320 "Initializing combo PHY %c (Voltage/Process Info : %s)\n", in icl_combo_phys_init()
321 phy_name(phy), procmon->name); in icl_combo_phys_init()
323 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
327 * EHL's combo PHY A can be hooked up to either an external in icl_combo_phys_init()
330 * can't be changed on the fly, so initialize the PHY's mux in icl_combo_phys_init()
334 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
336 phy == PHY_A) { in icl_combo_phys_init()
344 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
348 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
352 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
354 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
357 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
360 icl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
362 if (phy_is_master(dev_priv, phy)) in icl_combo_phys_init()
363 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
366 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
367 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
374 enum phy phy; in icl_combo_phys_uninit() local
376 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
377 if (phy == PHY_A && in icl_combo_phys_uninit()
378 !icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_uninit()
386 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
387 phy_name(phy)); in icl_combo_phys_uninit()
390 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
391 phy_name(phy)); in icl_combo_phys_uninit()
395 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
398 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
402 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()