Lines Matching full:divider
513 * CCK divider into the Punit register. in vlv_calc_voltage_level()
627 u32 divider; in vlv_set_cdclk() local
629 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
632 /* adjust cdclk divider */ in vlv_set_cdclk()
635 val |= divider; in vlv_set_cdclk()
639 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_set_cdclk()
1230 u8 divider; /* CD2X divider * 2 */ member
1235 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1239 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1244 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1246 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1251 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1252 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1253 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1254 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1255 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1256 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1258 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1259 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1260 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1261 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1262 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1263 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1265 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1266 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1267 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1268 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1269 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1270 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1275 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1276 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1277 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1278 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1279 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1280 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1282 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1283 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1284 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1285 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1286 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1287 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1289 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1290 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1291 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1292 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1293 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1294 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1299 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1300 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1301 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1303 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1304 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1305 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1307 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1308 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1309 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1314 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1315 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1316 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1317 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1318 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1320 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1321 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1322 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1323 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1324 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1326 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1327 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1328 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1329 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1330 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1335 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1336 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1337 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1338 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1339 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1340 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1342 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1343 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1344 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1345 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1346 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1347 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1349 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1350 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1351 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1352 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1353 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1354 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1359 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1360 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1361 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1362 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1363 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1364 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1365 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1366 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1367 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1368 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1369 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1370 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1371 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1376 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1377 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1378 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1379 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1380 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1381 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1386 { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
1387 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1388 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1389 { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
1390 { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
1391 { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
1392 { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
1393 { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
1394 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
1395 { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
1396 { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
1397 { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
1398 { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
1399 { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
1400 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
1401 { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
1402 { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
1403 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
1404 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1405 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1406 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1582 u32 divider; in bxt_get_cdclk() local
1599 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1601 switch (divider) { in bxt_get_cdclk()
1615 MISSING_CASE(divider); in bxt_get_cdclk()
2077 /* Figure out what CD2X divider we should be using for this cdclk */ in bxt_sanitize_cdclk()
2209 * The vco and cd2x divider will change independently in intel_cdclk_can_crawl()
2227 * to differentiate squasher vs. cd2x divider properly. For in intel_cdclk_can_squash()
2229 * divider. in intel_cdclk_can_squash()
2260 * configurations requires only a cd2x divider update
2267 * can be done with just a cd2x divider update, false if not.
2279 * to differentiate squasher vs. cd2x divider properly. For in intel_cdclk_can_cd2x_update()
2281 * divider. in intel_cdclk_can_cd2x_update()
2786 * by changing the cd2x divider (see glk_cdclk_table[]) and in intel_compute_min_cdclk()
3208 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
3354 * "Program Numerator=2, Denominator=4, Divider=37 decimal." in dg1_rawclk()
3365 int divider, fraction; in cnp_rawclk() local
3369 divider = 24000; in cnp_rawclk()
3373 divider = 19000; in cnp_rawclk()
3377 rawclk = CNP_RAWCLK_DIV(divider / 1000); in cnp_rawclk()
3388 return divider + fraction; in cnp_rawclk()