Lines Matching +full:tras +full:- +full:min
1 // SPDX-License-Identifier: MIT
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); in dg1_mchbar_read_qgv_point_info()
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in dg1_mchbar_read_qgv_point_info()
57 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
59 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
60 return -EINVAL; in dg1_mchbar_read_qgv_point_info()
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); in dg1_mchbar_read_qgv_point_info()
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
66 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); in dg1_mchbar_read_qgv_point_info()
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
70 sp->t_rc = sp->t_rp + sp->t_ras; in dg1_mchbar_read_qgv_point_info()
83 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_qgv_point_info()
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
92 sp->t_rp = (val & 0xff0000) >> 16; in icl_pcode_read_qgv_point_info()
93 sp->t_rcd = (val & 0xff000000) >> 24; in icl_pcode_read_qgv_point_info()
95 sp->t_rdpre = val2 & 0xff; in icl_pcode_read_qgv_point_info()
96 sp->t_ras = (val2 & 0xff00) >> 8; in icl_pcode_read_qgv_point_info()
98 sp->t_rc = sp->t_rp + sp->t_ras; in icl_pcode_read_qgv_point_info()
110 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in adls_pcode_read_psf_gv_point_info()
125 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
126 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_qgv_points_mask()
135 qgv_points = GENMASK(num_qgv_points - 1, 0); in icl_qgv_points_mask()
138 psf_points = GENMASK(num_psf_gv_points - 1, 0); in icl_qgv_points_mask()
158 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, in icl_pcode_restrict_qgv_points()
165 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask); in icl_pcode_restrict_qgv_points()
169 dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ? in icl_pcode_restrict_qgv_points()
181 val = intel_uncore_read(&dev_priv->uncore, in mtl_read_qgv_point_info()
183 val2 = intel_uncore_read(&dev_priv->uncore, in mtl_read_qgv_point_info()
186 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
187 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
188 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
190 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
191 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
193 sp->t_rc = sp->t_rp + sp->t_ras; in mtl_read_qgv_point_info()
215 const struct dram_info *dram_info = &dev_priv->dram_info; in icl_get_qgv_points()
218 qi->num_points = dram_info->num_qgv_points; in icl_get_qgv_points()
219 qi->num_psf_points = dram_info->num_psf_gv_points; in icl_get_qgv_points()
222 switch (dram_info->type) { in icl_get_qgv_points()
224 qi->t_bl = 4; in icl_get_qgv_points()
225 qi->max_numchannels = 2; in icl_get_qgv_points()
226 qi->channel_width = 64; in icl_get_qgv_points()
227 qi->deinterleave = 2; in icl_get_qgv_points()
230 qi->t_bl = 8; in icl_get_qgv_points()
231 qi->max_numchannels = 4; in icl_get_qgv_points()
232 qi->channel_width = 32; in icl_get_qgv_points()
233 qi->deinterleave = 2; in icl_get_qgv_points()
237 qi->t_bl = 16; in icl_get_qgv_points()
238 qi->max_numchannels = 8; in icl_get_qgv_points()
239 qi->channel_width = 16; in icl_get_qgv_points()
240 qi->deinterleave = 4; in icl_get_qgv_points()
243 MISSING_CASE(dram_info->type); in icl_get_qgv_points()
244 return -EINVAL; in icl_get_qgv_points()
247 switch (dram_info->type) { in icl_get_qgv_points()
249 qi->t_bl = is_y_tile ? 8 : 4; in icl_get_qgv_points()
250 qi->max_numchannels = 2; in icl_get_qgv_points()
251 qi->channel_width = 64; in icl_get_qgv_points()
252 qi->deinterleave = is_y_tile ? 1 : 2; in icl_get_qgv_points()
255 qi->t_bl = is_y_tile ? 16 : 8; in icl_get_qgv_points()
256 qi->max_numchannels = 4; in icl_get_qgv_points()
257 qi->channel_width = 32; in icl_get_qgv_points()
258 qi->deinterleave = is_y_tile ? 1 : 2; in icl_get_qgv_points()
262 qi->t_bl = 8; in icl_get_qgv_points()
263 qi->max_numchannels = 4; in icl_get_qgv_points()
264 qi->channel_width = 32; in icl_get_qgv_points()
265 qi->deinterleave = 2; in icl_get_qgv_points()
270 qi->t_bl = 16; in icl_get_qgv_points()
271 qi->max_numchannels = 8; in icl_get_qgv_points()
272 qi->channel_width = 16; in icl_get_qgv_points()
273 qi->deinterleave = is_y_tile ? 2 : 4; in icl_get_qgv_points()
276 qi->t_bl = 16; in icl_get_qgv_points()
277 qi->max_numchannels = 1; in icl_get_qgv_points()
281 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; in icl_get_qgv_points()
282 qi->max_numchannels = 1; in icl_get_qgv_points()
285 if (drm_WARN_ON(&dev_priv->drm, in icl_get_qgv_points()
286 qi->num_points > ARRAY_SIZE(qi->points))) in icl_get_qgv_points()
287 qi->num_points = ARRAY_SIZE(qi->points); in icl_get_qgv_points()
289 for (i = 0; i < qi->num_points; i++) { in icl_get_qgv_points()
290 struct intel_qgv_point *sp = &qi->points[i]; in icl_get_qgv_points()
296 drm_dbg_kms(&dev_priv->drm, in icl_get_qgv_points()
297 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", in icl_get_qgv_points()
298 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, in icl_get_qgv_points()
299 sp->t_rcd, sp->t_rc); in icl_get_qgv_points()
302 if (qi->num_psf_points > 0) { in icl_get_qgv_points()
303 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points); in icl_get_qgv_points()
305 …drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandw… in icl_get_qgv_points()
306 qi->num_psf_points = 0; in icl_get_qgv_points()
309 for (i = 0; i < qi->num_psf_points; i++) in icl_get_qgv_points()
310 drm_dbg_kms(&dev_priv->drm, in icl_get_qgv_points()
312 i, qi->psf_points[i].clk); in icl_get_qgv_points()
333 for (i = 0; i < qi->num_points; i++) in icl_sagv_max_dclk()
334 dclk = max(dclk, qi->points[i].dclk); in icl_sagv_max_dclk()
390 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in icl_get_bw_info()
394 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in icl_get_bw_info()
399 drm_dbg_kms(&dev_priv->drm, in icl_get_bw_info()
405 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); in icl_get_bw_info()
406 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); in icl_get_bw_info()
410 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in icl_get_bw_info()
414 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; in icl_get_bw_info()
415 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; in icl_get_bw_info()
417 bi->num_qgv_points = qi.num_points; in icl_get_bw_info()
418 bi->num_psf_gv_points = qi.num_psf_points; in icl_get_bw_info()
430 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + in icl_get_bw_info()
431 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); in icl_get_bw_info()
432 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in icl_get_bw_info()
434 bi->deratedbw[j] = min(maxdebw, in icl_get_bw_info()
435 bw * (100 - sa->derating) / 100); in icl_get_bw_info()
437 drm_dbg_kms(&dev_priv->drm, in icl_get_bw_info()
439 i, j, bi->num_planes, bi->deratedbw[j]); in icl_get_bw_info()
448 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in icl_get_bw_info()
450 dev_priv->display.sagv.status = I915_SAGV_ENABLED; in icl_get_bw_info()
458 const struct dram_info *dram_info = &dev_priv->dram_info; in tgl_get_bw_info()
460 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in tgl_get_bw_info()
465 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in tgl_get_bw_info()
470 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
476 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)) in tgl_get_bw_info()
485 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels."); in tgl_get_bw_info()
492 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */ in tgl_get_bw_info()
494 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); in tgl_get_bw_info()
502 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in tgl_get_bw_info()
507 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; in tgl_get_bw_info()
509 if (i < num_groups - 1) { in tgl_get_bw_info()
510 bi_next = &dev_priv->display.bw.max[i + 1]; in tgl_get_bw_info()
513 bi_next->num_planes = (ipqdepth - clpchgroup) / in tgl_get_bw_info()
516 bi_next->num_planes = 0; in tgl_get_bw_info()
519 bi->num_qgv_points = qi.num_points; in tgl_get_bw_info()
520 bi->num_psf_gv_points = qi.num_psf_points; in tgl_get_bw_info()
532 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + in tgl_get_bw_info()
533 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); in tgl_get_bw_info()
534 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in tgl_get_bw_info()
536 bi->deratedbw[j] = min(maxdebw, in tgl_get_bw_info()
537 bw * (100 - sa->derating) / 100); in tgl_get_bw_info()
538 bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk * in tgl_get_bw_info()
542 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
544 i, j, bi->num_planes, bi->deratedbw[j], in tgl_get_bw_info()
545 bi->peakbw[j]); in tgl_get_bw_info()
551 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk); in tgl_get_bw_info()
553 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
555 i, j, bi->num_planes, bi->psf_bw[j]); in tgl_get_bw_info()
565 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in tgl_get_bw_info()
567 dev_priv->display.sagv.status = I915_SAGV_ENABLED; in tgl_get_bw_info()
575 int num_groups = ARRAY_SIZE(i915->display.bw.max); in dg2_get_bw_info()
582 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth, in dg2_get_bw_info()
583 * whereas DG2-G11 platforms have 38 GB/s. in dg2_get_bw_info()
586 struct intel_bw_info *bi = &i915->display.bw.max[i]; in dg2_get_bw_info()
588 bi->num_planes = 1; in dg2_get_bw_info()
590 bi->num_qgv_points = 1; in dg2_get_bw_info()
591 bi->deratedbw[0] = deratedbw; in dg2_get_bw_info()
594 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in dg2_get_bw_info()
607 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) { in icl_max_bw_index()
609 &dev_priv->display.bw.max[i]; in icl_max_bw_index()
613 * SAGV is forced to off/min/med/max. in icl_max_bw_index()
615 if (qgv_point >= bi->num_qgv_points) in icl_max_bw_index()
618 if (num_planes >= bi->num_planes) in icl_max_bw_index()
635 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) { in tgl_max_bw_index()
637 &dev_priv->display.bw.max[i]; in tgl_max_bw_index()
641 * SAGV is forced to off/min/med/max. in tgl_max_bw_index()
643 if (qgv_point >= bi->num_qgv_points) in tgl_max_bw_index()
646 if (num_planes <= bi->num_planes) in tgl_max_bw_index()
657 &dev_priv->display.bw.max[0]; in adl_psf_bw()
659 return bi->psf_bw[psf_gv_point]; in adl_psf_bw()
689 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); in intel_bw_crtc_num_active_planes()
694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_data_rate()
695 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_data_rate()
707 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
710 data_rate += crtc_state->data_rate_y[plane_id]; in intel_bw_crtc_data_rate()
719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_min_cdclk()
720 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_min_cdclk()
731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_update()
732 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_update()
734 bw_state->data_rate[crtc->pipe] = in intel_bw_crtc_update()
736 bw_state->num_active_planes[crtc->pipe] = in intel_bw_crtc_update()
739 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n", in intel_bw_crtc_update()
740 pipe_name(crtc->pipe), in intel_bw_crtc_update()
741 bw_state->data_rate[crtc->pipe], in intel_bw_crtc_update()
742 bw_state->num_active_planes[crtc->pipe]); in intel_bw_crtc_update()
752 num_active_planes += bw_state->num_active_planes[pipe]; in intel_bw_num_active_planes()
764 data_rate += bw_state->data_rate[pipe]; in intel_bw_data_rate()
775 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_old_bw_state()
778 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_old_bw_state()
786 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_new_bw_state()
789 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_new_bw_state()
797 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_bw_state()
800 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_bw_state()
813 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in mtl_find_qgv_points()
818 ret = intel_atomic_lock_global_state(&new_bw_state->base); in mtl_find_qgv_points()
828 new_bw_state->qgv_point_peakbw = U16_MAX; in mtl_find_qgv_points()
829 drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw."); in mtl_find_qgv_points()
842 if (bw_index >= ARRAY_SIZE(i915->display.bw.max)) in mtl_find_qgv_points()
845 max_data_rate = i915->display.bw.max[bw_index].deratedbw[i]; in mtl_find_qgv_points()
850 if (max_data_rate - data_rate < best_rate) { in mtl_find_qgv_points()
851 best_rate = max_data_rate - data_rate; in mtl_find_qgv_points()
852 qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i]; in mtl_find_qgv_points()
855 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n", in mtl_find_qgv_points()
859 drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n", in mtl_find_qgv_points()
867 drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n", in mtl_find_qgv_points()
869 return -EINVAL; in mtl_find_qgv_points()
873 new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100); in mtl_find_qgv_points()
886 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_find_qgv_points()
887 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_find_qgv_points()
893 ret = intel_atomic_lock_global_state(&new_bw_state->base); in icl_find_qgv_points()
906 if (idx >= ARRAY_SIZE(i915->display.bw.max)) in icl_find_qgv_points()
909 max_data_rate = i915->display.bw.max[idx].deratedbw[i]; in icl_find_qgv_points()
926 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n", in icl_find_qgv_points()
936 drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d" in icl_find_qgv_points()
943 * left, so if we couldn't - simply reject the configuration for obvious in icl_find_qgv_points()
947 drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory" in icl_find_qgv_points()
950 return -EINVAL; in icl_find_qgv_points()
954 drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory" in icl_find_qgv_points()
957 return -EINVAL; in icl_find_qgv_points()
967 drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n", in icl_find_qgv_points()
975 new_bw_state->qgv_points_mask = in icl_find_qgv_points()
984 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) { in icl_find_qgv_points()
985 ret = intel_atomic_serialize_global_state(&new_bw_state->base); in icl_find_qgv_points()
1019 &old_bw_state->dbuf_bw[pipe]; in intel_bw_state_changed()
1021 &new_bw_state->dbuf_bw[pipe]; in intel_bw_state_changed()
1025 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] || in intel_bw_state_changed()
1026 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice]) in intel_bw_state_changed()
1030 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe]) in intel_bw_state_changed()
1043 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_plane_calc_dbuf_bw()
1044 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; in skl_plane_calc_dbuf_bw()
1053 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate); in skl_plane_calc_dbuf_bw()
1054 crtc_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1061 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_crtc_calc_dbuf_bw()
1062 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_calc_dbuf_bw()
1063 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; in skl_crtc_calc_dbuf_bw()
1068 if (!crtc_state->hw.active) in skl_crtc_calc_dbuf_bw()
1080 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
1081 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
1085 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
1086 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
1108 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; in intel_bw_dbuf_min_cdclk()
1110 max_bw = max(crtc_bw->max_bw[slice], max_bw); in intel_bw_dbuf_min_cdclk()
1111 num_active_planes += hweight8(crtc_bw->active_planes[slice]); in intel_bw_dbuf_min_cdclk()
1130 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk); in intel_bw_min_cdclk()
1138 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_bw_calc_min_cdclk()
1159 new_bw_state->min_cdclk[crtc->pipe] = in intel_bw_calc_min_cdclk()
1167 int ret = intel_atomic_lock_global_state(&new_bw_state->base); in intel_bw_calc_min_cdclk()
1177 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1192 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1198 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()
1201 drm_dbg_kms(&dev_priv->drm, in intel_bw_calc_min_cdclk()
1202 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
1203 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
1211 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bw_check_data_rate()
1240 new_bw_state->data_rate[crtc->pipe] = new_data_rate; in intel_bw_check_data_rate()
1241 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes; in intel_bw_check_data_rate()
1245 drm_dbg_kms(&i915->drm, in intel_bw_check_data_rate()
1247 crtc->base.base.id, crtc->base.name, in intel_bw_check_data_rate()
1248 new_bw_state->data_rate[crtc->pipe], in intel_bw_check_data_rate()
1249 new_bw_state->num_active_planes[crtc->pipe]); in intel_bw_check_data_rate()
1258 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bw_atomic_check()
1298 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in intel_bw_duplicate_state()
1302 return &state->base; in intel_bw_duplicate_state()
1322 return -ENOMEM; in intel_bw_init()
1324 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj, in intel_bw_init()
1325 &state->base, &intel_bw_funcs); in intel_bw_init()