Lines Matching full:plane
25 * DOC: atomic plane helpers
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
54 struct intel_plane *plane) in intel_plane_state_reset() argument
58 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); in intel_plane_state_reset()
66 struct intel_plane *plane; in intel_plane_alloc() local
68 plane = kzalloc(sizeof(*plane), GFP_KERNEL); in intel_plane_alloc()
69 if (!plane) in intel_plane_alloc()
74 kfree(plane); in intel_plane_alloc()
78 intel_plane_state_reset(plane_state, plane); in intel_plane_alloc()
80 plane->base.state = &plane_state->uapi; in intel_plane_alloc()
82 return plane; in intel_plane_alloc()
85 void intel_plane_free(struct intel_plane *plane) in intel_plane_free() argument
87 intel_plane_destroy_state(&plane->base, plane->base.state); in intel_plane_free()
88 kfree(plane); in intel_plane_free()
92 * intel_plane_duplicate_state - duplicate plane state
93 * @plane: drm plane
95 * Allocates and returns a copy of the plane state (both common and
96 * Intel-specific) for the specified plane.
98 * Returns: The newly allocated plane state, or NULL on failure.
101 intel_plane_duplicate_state(struct drm_plane *plane) in intel_plane_duplicate_state() argument
105 intel_state = to_intel_plane_state(plane->state); in intel_plane_duplicate_state()
111 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi); in intel_plane_duplicate_state()
125 * intel_plane_destroy_state - destroy plane state
126 * @plane: drm plane
129 * Destroys the plane state (both common and Intel-specific) for the
130 * specified plane.
133 intel_plane_destroy_state(struct drm_plane *plane, in intel_plane_destroy_state() argument
138 drm_WARN_ON(plane->dev, plane_state->ggtt_vma); in intel_plane_destroy_state()
139 drm_WARN_ON(plane->dev, plane_state->dpt_vma); in intel_plane_destroy_state()
170 * Note we don't check for plane visibility here as in intel_plane_pixel_rate()
201 struct intel_plane *plane) in use_min_ddb() argument
203 struct drm_i915_private *i915 = to_i915(plane->base.dev); in use_min_ddb()
207 plane->async_flip; in use_min_ddb()
215 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_relative_data_rate() local
224 * We calculate extra ddb based on ratio plane rate/total data rate in intel_plane_relative_data_rate()
225 * in case, in some cases we should not allocate extra ddb for the plane, in intel_plane_relative_data_rate()
228 if (use_min_ddb(crtc_state, plane)) in intel_plane_relative_data_rate()
233 * the 90/270 degree plane rotation cases (to match the in intel_plane_relative_data_rate()
239 /* UV plane does 1/2 pixel sub-sampling */ in intel_plane_relative_data_rate()
247 if (plane->id == PLANE_CURSOR) in intel_plane_relative_data_rate()
256 struct intel_plane *plane, in intel_plane_calc_min_cdclk() argument
259 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_calc_min_cdclk()
261 intel_atomic_get_new_plane_state(state, plane); in intel_plane_calc_min_cdclk()
267 if (!plane_state->uapi.visible || !plane->min_cdclk) in intel_plane_calc_min_cdclk()
273 new_crtc_state->min_cdclk[plane->id] = in intel_plane_calc_min_cdclk()
274 plane->min_cdclk(new_crtc_state, plane_state); in intel_plane_calc_min_cdclk()
278 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
280 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
284 if (new_crtc_state->min_cdclk[plane->id] <= in intel_plane_calc_min_cdclk()
285 old_crtc_state->min_cdclk[plane->id]) in intel_plane_calc_min_cdclk()
296 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
300 if (new_crtc_state->min_cdclk[plane->id] <= in intel_plane_calc_min_cdclk()
305 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
306 plane->base.base.id, plane->base.name, in intel_plane_calc_min_cdclk()
307 new_crtc_state->min_cdclk[plane->id], in intel_plane_calc_min_cdclk()
333 * the plane is logically enabled on the uapi level. in intel_plane_copy_uapi_to_hw_state()
368 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_set_invisible() local
370 crtc_state->active_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
371 crtc_state->scaled_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
372 crtc_state->nv12_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
373 crtc_state->c8_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
374 crtc_state->async_flip_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
375 crtc_state->data_rate[plane->id] = 0; in intel_plane_set_invisible()
376 crtc_state->data_rate_y[plane->id] = 0; in intel_plane_set_invisible()
377 crtc_state->rel_data_rate[plane->id] = 0; in intel_plane_set_invisible()
378 crtc_state->rel_data_rate_y[plane->id] = 0; in intel_plane_set_invisible()
379 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_set_invisible()
416 static bool intel_plane_do_async_flip(struct intel_plane *plane, in intel_plane_do_async_flip() argument
420 struct drm_i915_private *i915 = to_i915(plane->base.dev); in intel_plane_do_async_flip()
422 if (!plane->async_flip) in intel_plane_do_async_flip()
442 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in i9xx_must_disable_cxsr() local
449 if (plane->id == PLANE_CURSOR) in i9xx_must_disable_cxsr()
456 /* Must disable CxSR around plane enable/disable */ in i9xx_must_disable_cxsr()
464 * Most plane control register updates are blocked while in CxSR. in i9xx_must_disable_cxsr()
466 * Tiling mode is one exception where the primary plane can in i9xx_must_disable_cxsr()
471 if (plane->id == PLANE_PRIMARY) { in i9xx_must_disable_cxsr()
485 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in intel_plane_atomic_calc_changes() local
493 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
512 * per-plane wm computation to the .check_plane() hook, and in intel_plane_atomic_calc_changes()
527 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", in intel_plane_atomic_calc_changes()
529 plane->base.base.id, plane->base.name, in intel_plane_atomic_calc_changes()
548 new_crtc_state->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
558 * plane will be internally buffered and delayed while Big FIFO in intel_plane_atomic_calc_changes()
585 * plane, not only sprite plane. in intel_plane_atomic_calc_changes()
587 if (plane->id != PLANE_CURSOR && in intel_plane_atomic_calc_changes()
594 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { in intel_plane_atomic_calc_changes()
596 new_crtc_state->async_flip_planes |= BIT(plane->id); in intel_plane_atomic_calc_changes()
607 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in intel_plane_atomic_check_with_state() local
612 new_crtc_state->enabled_planes &= ~BIT(plane->id); in intel_plane_atomic_check_with_state()
617 ret = plane->check_plane(new_crtc_state, new_plane_state); in intel_plane_atomic_check_with_state()
622 new_crtc_state->enabled_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
626 new_crtc_state->active_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
630 new_crtc_state->scaled_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
634 new_crtc_state->nv12_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
638 new_crtc_state->c8_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
641 new_crtc_state->update_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
645 new_crtc_state->data_rate_y[plane->id] = in intel_plane_atomic_check_with_state()
647 new_crtc_state->data_rate[plane->id] = in intel_plane_atomic_check_with_state()
650 new_crtc_state->rel_data_rate_y[plane->id] = in intel_plane_atomic_check_with_state()
653 new_crtc_state->rel_data_rate[plane->id] = in intel_plane_atomic_check_with_state()
657 new_crtc_state->data_rate[plane->id] = in intel_plane_atomic_check_with_state()
660 new_crtc_state->rel_data_rate[plane->id] = in intel_plane_atomic_check_with_state()
673 struct intel_plane *plane; in intel_crtc_get_plane() local
675 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in intel_crtc_get_plane()
676 if (plane->id == plane_id) in intel_crtc_get_plane()
677 return plane; in intel_crtc_get_plane()
684 struct intel_plane *plane) in intel_plane_atomic_check() argument
688 intel_atomic_get_new_plane_state(state, plane); in intel_plane_atomic_check()
690 intel_atomic_get_old_plane_state(state, plane); in intel_plane_atomic_check()
692 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe); in intel_plane_atomic_check()
702 intel_crtc_get_plane(master_crtc, plane->id); in intel_plane_atomic_check()
734 struct intel_plane *plane; in skl_next_plane_to_commit() local
740 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { in skl_next_plane_to_commit()
741 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit()
743 if (crtc->pipe != plane->pipe || in skl_next_plane_to_commit()
757 return plane; in skl_next_plane_to_commit()
766 void intel_plane_update_noarm(struct intel_plane *plane, in intel_plane_update_noarm() argument
772 trace_intel_plane_update_noarm(plane, crtc); in intel_plane_update_noarm()
774 if (plane->update_noarm) in intel_plane_update_noarm()
775 plane->update_noarm(plane, crtc_state, plane_state); in intel_plane_update_noarm()
778 void intel_plane_update_arm(struct intel_plane *plane, in intel_plane_update_arm() argument
784 trace_intel_plane_update_arm(plane, crtc); in intel_plane_update_arm()
786 if (crtc_state->do_async_flip && plane->async_flip) in intel_plane_update_arm()
787 plane->async_flip(plane, crtc_state, plane_state, true); in intel_plane_update_arm()
789 plane->update_arm(plane, crtc_state, plane_state); in intel_plane_update_arm()
792 void intel_plane_disable_arm(struct intel_plane *plane, in intel_plane_disable_arm() argument
797 trace_intel_plane_disable_arm(plane, crtc); in intel_plane_disable_arm()
798 plane->disable_arm(plane, crtc_state); in intel_plane_disable_arm()
808 struct intel_plane *plane; in intel_crtc_planes_update_noarm() local
818 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { in intel_crtc_planes_update_noarm()
819 if (crtc->pipe != plane->pipe || in intel_crtc_planes_update_noarm()
820 !(update_mask & BIT(plane->id))) in intel_crtc_planes_update_noarm()
826 intel_plane_update_noarm(plane, new_crtc_state, new_plane_state); in intel_crtc_planes_update_noarm()
840 struct intel_plane *plane; in skl_crtc_planes_update_arm() local
847 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) { in skl_crtc_planes_update_arm()
849 intel_atomic_get_new_plane_state(state, plane); in skl_crtc_planes_update_arm()
857 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); in skl_crtc_planes_update_arm()
859 intel_plane_disable_arm(plane, new_crtc_state); in skl_crtc_planes_update_arm()
870 struct intel_plane *plane; in i9xx_crtc_planes_update_arm() local
873 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { in i9xx_crtc_planes_update_arm()
874 if (crtc->pipe != plane->pipe || in i9xx_crtc_planes_update_arm()
875 !(update_mask & BIT(plane->id))) in i9xx_crtc_planes_update_arm()
883 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); in i9xx_crtc_planes_update_arm()
885 intel_plane_disable_arm(plane, new_crtc_state); in i9xx_crtc_planes_update_arm()
905 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in intel_atomic_plane_check_clipping()
924 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n"); in intel_atomic_plane_check_clipping()
940 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n"); in intel_atomic_plane_check_clipping()
946 /* final plane coordinates will be relative to the plane's pipe */ in intel_atomic_plane_check_clipping()
954 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in intel_plane_check_src_coordinates()
1054 * intel_prepare_plane_fb - Prepare fb for usage on plane
1055 * @_plane: drm plane to prepare for
1056 * @_new_plane_state: the plane state being prepared
1058 * Prepares a framebuffer for usage on a display plane. Generally this
1070 struct intel_plane *plane = to_intel_plane(_plane); in intel_prepare_plane_fb() local
1075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_prepare_plane_fb()
1077 intel_atomic_get_old_plane_state(state, plane); in intel_prepare_plane_fb()
1113 ret = drm_gem_plane_helper_prepare_fb(&plane->base, &new_plane_state->uapi); in intel_prepare_plane_fb()
1144 * intel_cleanup_plane_fb - Cleans up an fb after plane use
1145 * @plane: drm plane to clean up for
1148 * Cleans up a framebuffer that has just been removed from a plane.
1151 intel_cleanup_plane_fb(struct drm_plane *plane, in intel_cleanup_plane_fb() argument
1158 struct drm_i915_private *dev_priv = to_i915(plane->dev); in intel_cleanup_plane_fb()
1175 void intel_plane_helper_add(struct intel_plane *plane) in intel_plane_helper_add() argument
1177 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); in intel_plane_helper_add()