Lines Matching +full:dual +full:- +full:lane
75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
79 int lane) in dp_get_lane_status() argument
81 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
82 int s = (lane & 1) * 4; in dp_get_lane_status()
93 int lane; in drm_dp_channel_eq_ok() local
99 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
100 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
111 int lane; in drm_dp_clock_recovery_ok() local
114 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
115 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
124 int lane) in drm_dp_get_adjust_request_voltage() argument
126 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in drm_dp_get_adjust_request_voltage()
127 int s = ((lane & 1) ? in drm_dp_get_adjust_request_voltage()
137 int lane) in drm_dp_get_adjust_request_pre_emphasis() argument
139 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in drm_dp_get_adjust_request_pre_emphasis()
140 int s = ((lane & 1) ? in drm_dp_get_adjust_request_pre_emphasis()
151 int lane) in drm_dp_get_adjust_tx_ffe_preset() argument
153 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in drm_dp_get_adjust_tx_ffe_preset()
154 int s = ((lane & 1) ? in drm_dp_get_adjust_tx_ffe_preset()
168 int lane; in drm_dp_128b132b_lane_channel_eq_done() local
174 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_channel_eq_done()
175 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_128b132b_lane_channel_eq_done()
188 int lane; in drm_dp_128b132b_lane_symbol_locked() local
190 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_symbol_locked()
191 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_128b132b_lane_symbol_locked()
229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
230 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
242 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
255 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
277 * - Clock recovery vs. channel equalization
278 * - DPRX vs. LTTPR
279 * - 128b/132b vs. 8b/10b
280 * - DPCD rev 1.3 vs. later
329 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", in __read_delay()
330 aux->name); in __read_delay()
360 drm_err(aux->drm_dev, "%s: failed rd interval read\n", in drm_dp_128b132b_read_aux_rd_interval()
361 aux->name); in drm_dp_128b132b_read_aux_rd_interval()
407 * drm_dp_phy_name() - Get the name of the given DP PHY
412 * non-NULL and valid.
446 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; in dp_lttpr_phy_cap()
498 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; in drm_dp_dump_access()
501 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", in drm_dp_dump_access()
502 aux->name, offset, arrow, ret, min(ret, 20), buffer); in drm_dp_dump_access()
504 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", in drm_dp_dump_access()
505 aux->name, offset, arrow, ret); in drm_dp_dump_access()
511 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
515 * Transactions are described using a hardware-independent drm_dp_aux_msg
517 * Both native and I2C-over-AUX transactions are supported.
533 mutex_lock(&aux->hw_mutex); in drm_dp_dpcd_access()
542 if (ret != 0 && ret != -ETIMEDOUT) { in drm_dp_dpcd_access()
547 ret = aux->transfer(aux, &msg); in drm_dp_dpcd_access()
554 ret = -EPROTO; in drm_dp_dpcd_access()
556 ret = -EIO; in drm_dp_dpcd_access()
568 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", in drm_dp_dpcd_access()
569 aux->name, err); in drm_dp_dpcd_access()
573 mutex_unlock(&aux->hw_mutex); in drm_dp_dpcd_access()
578 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
583 * be used to trigger some side-effect the read access has, like waking up the
584 * sink, without the need for the read-out value.
603 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
610 * code on failure. -EIO is returned if the request was NAKed by the sink or
612 * function returns -EPROTO. Errors from the underlying AUX channel transfer
613 * function, with the exception of -EBUSY (which causes the transaction to
626 * gets woken up and subsequently re-enters power save mode. in drm_dp_dpcd_read()
633 if (!aux->is_remote) { in drm_dp_dpcd_read()
639 if (aux->is_remote) in drm_dp_dpcd_read()
651 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
658 * code on failure. -EIO is returned if the request was NAKed by the sink or
660 * function returns -EPROTO. Errors from the underlying AUX channel transfer
661 * function, with the exception of -EBUSY (which causes the transaction to
669 if (aux->is_remote) in drm_dp_dpcd_write()
681 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
697 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
732 DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
737 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
740 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], in drm_dp_dpcd_read_phy_link_status()
741 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], in drm_dp_dpcd_read_phy_link_status()
742 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); in drm_dp_dpcd_read_phy_link_status()
743 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; in drm_dp_dpcd_read_phy_link_status()
754 return edid && edid->revision >= 4 && in is_edid_digital_input_dp()
755 edid->input & DRM_EDID_INPUT_DIGITAL && in is_edid_digital_input_dp()
756 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; in is_edid_digital_input_dp()
760 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
782 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
817 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
831 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
832 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
838 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
839 aux->name, DP_TEST_REQUEST); in drm_dp_send_real_edid_checksum()
845 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", in drm_dp_send_real_edid_checksum()
846 aux->name); in drm_dp_send_real_edid_checksum()
852 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
853 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
860 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
861 aux->name, DP_TEST_EDID_CHECKSUM); in drm_dp_send_real_edid_checksum()
867 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
868 aux->name, DP_TEST_RESPONSE); in drm_dp_send_real_edid_checksum()
908 return -EIO; in drm_dp_read_extended_dpcd_caps()
911 drm_dbg_kms(aux->drm_dev, in drm_dp_read_extended_dpcd_caps()
913 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
920 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
928 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
949 return -EIO; in drm_dp_read_dpcd_caps()
955 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
962 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
1002 return -EIO; in drm_dp_read_downstream_info()
1004 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); in drm_dp_read_downstream_info()
1011 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1039 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1069 * DP dual mode adapter's max TMDS clock. in drm_dp_downstream_max_tmds_clock()
1072 * may not fordward that the DP dual mode i2c in drm_dp_downstream_max_tmds_clock()
1095 /* FIXME what to do about DVI dual link? */ in drm_dp_downstream_max_tmds_clock()
1104 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1147 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1204 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1205 * YCbCr 4:2:0 pass-through capability
1235 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1236 * YCbCr 4:4:4->4:2:0 conversion capability
1264 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1265 * RGB->YCbCr conversion capability
1270 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1296 * drm_dp_downstream_mode() - return a mode for downstream facing port
1351 * drm_dp_downstream_id() - identify branch device
1364 * drm_dp_downstream_debug() - debug DP branch devices
1455 * drm_dp_subconnector_type() - get DP branch device type
1473 /* Can be HDMI or DVI-D, DVI-D is a safer option */ in drm_dp_subconnector_type()
1476 /* Can be VGA or DVI-A, VGA is more popular */ in drm_dp_subconnector_type()
1507 * drm_dp_set_subconnector_property - set subconnector for DP connector
1524 drm_object_property_set_value(&connector->base, in drm_dp_set_subconnector_property()
1525 connector->dev->mode_config.dp_subconnector_property, in drm_dp_set_subconnector_property()
1531 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1547 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && in drm_dp_read_sink_count_cap()
1555 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1572 return -EIO; in drm_dp_read_sink_count()
1579 * I2C-over-AUX implementation
1597 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { in drm_dp_i2c_msg_write_status_update()
1598 msg->request &= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_write_status_update()
1599 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; in drm_dp_i2c_msg_write_status_update()
1620 if ((msg->request & DP_AUX_I2C_READ) == 0) in drm_dp_aux_req_duration()
1621 len += msg->size * 8; in drm_dp_aux_req_duration()
1635 if (msg->request & DP_AUX_I2C_READ) in drm_dp_aux_reply_duration()
1636 len += msg->size * 8; in drm_dp_aux_reply_duration()
1659 msg->size * I2C_DATA_LEN + in drm_dp_i2c_msg_duration()
1685 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1688 * Transfer a single I2C-over-AUX message and handle various error conditions,
1709 ret = aux->transfer(aux, msg); in drm_dp_i2c_do_msg()
1711 if (ret == -EBUSY) in drm_dp_i2c_do_msg()
1717 * communicate with a non-existent DisplayPort device). in drm_dp_i2c_do_msg()
1720 if (ret == -ETIMEDOUT) in drm_dp_i2c_do_msg()
1721 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", in drm_dp_i2c_do_msg()
1722 aux->name); in drm_dp_i2c_do_msg()
1724 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", in drm_dp_i2c_do_msg()
1725 aux->name, ret); in drm_dp_i2c_do_msg()
1730 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { in drm_dp_i2c_do_msg()
1733 * For I2C-over-AUX transactions this isn't enough, we in drm_dp_i2c_do_msg()
1739 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1740 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1741 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1744 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); in drm_dp_i2c_do_msg()
1748 * more careful with DP-to-legacy adapters where a in drm_dp_i2c_do_msg()
1752 * safe for all use-cases. in drm_dp_i2c_do_msg()
1758 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", in drm_dp_i2c_do_msg()
1759 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1760 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1763 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { in drm_dp_i2c_do_msg()
1769 if (ret != msg->size) in drm_dp_i2c_do_msg()
1774 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1775 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1776 aux->i2c_nack_count++; in drm_dp_i2c_do_msg()
1777 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1780 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); in drm_dp_i2c_do_msg()
1785 aux->i2c_defer_count++; in drm_dp_i2c_do_msg()
1794 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", in drm_dp_i2c_do_msg()
1795 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1796 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1800 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); in drm_dp_i2c_do_msg()
1801 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1807 msg->request = (i2c_msg->flags & I2C_M_RD) ? in drm_dp_i2c_msg_set_request()
1809 if (!(i2c_msg->flags & I2C_M_STOP)) in drm_dp_i2c_msg_set_request()
1810 msg->request |= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_set_request()
1820 int err, ret = orig_msg->size; in drm_dp_i2c_drain_msg()
1826 return err == 0 ? -EPROTO : err; in drm_dp_i2c_drain_msg()
1829 drm_dbg_kms(aux->drm_dev, in drm_dp_i2c_drain_msg()
1831 aux->name, msg.size, err); in drm_dp_i2c_drain_msg()
1835 msg.size -= err; in drm_dp_i2c_drain_msg()
1843 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1850 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1855 struct drm_dp_aux *aux = adapter->algo_data; in drm_dp_i2c_xfer()
1891 msg.size = min(transfer_size, msgs[i].len - j); in drm_dp_i2c_xfer()
1934 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); in lock_bus()
1939 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); in trylock_bus()
1944 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); in unlock_bus()
1969 if (count == aux->crc_count) in drm_dp_aux_get_crc()
1970 return -EAGAIN; /* No CRC yet */ in drm_dp_aux_get_crc()
1972 aux->crc_count = count; in drm_dp_aux_get_crc()
1994 if (WARN_ON(!aux->crtc)) in drm_dp_aux_crc_work()
1997 crtc = aux->crtc; in drm_dp_aux_crc_work()
1998 while (crtc->crc.opened) { in drm_dp_aux_crc_work()
2000 if (!crtc->crc.opened) in drm_dp_aux_crc_work()
2004 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2009 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2010 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", in drm_dp_aux_crc_work()
2011 aux->name, ret); in drm_dp_aux_crc_work()
2014 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); in drm_dp_aux_crc_work()
2026 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2034 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_remote_aux_init()
2039 * drm_dp_aux_init() - minimally initialise an aux channel
2057 mutex_init(&aux->hw_mutex); in drm_dp_aux_init()
2058 mutex_init(&aux->cec.lock); in drm_dp_aux_init()
2059 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_aux_init()
2061 aux->ddc.algo = &drm_dp_i2c_algo; in drm_dp_aux_init()
2062 aux->ddc.algo_data = aux; in drm_dp_aux_init()
2063 aux->ddc.retries = 3; in drm_dp_aux_init()
2065 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; in drm_dp_aux_init()
2070 * drm_dp_aux_register() - initialise and register aux channel
2100 WARN_ON_ONCE(!aux->drm_dev); in drm_dp_aux_register()
2102 if (!aux->ddc.algo) in drm_dp_aux_register()
2105 aux->ddc.owner = THIS_MODULE; in drm_dp_aux_register()
2106 aux->ddc.dev.parent = aux->dev; in drm_dp_aux_register()
2108 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), in drm_dp_aux_register()
2109 sizeof(aux->ddc.name)); in drm_dp_aux_register()
2115 ret = i2c_add_adapter(&aux->ddc); in drm_dp_aux_register()
2126 * drm_dp_aux_unregister() - unregister an AUX adapter
2132 i2c_del_adapter(&aux->ddc); in drm_dp_aux_unregister()
2139 * drm_dp_psr_setup_time() - PSR setup in time usec
2161 return -EINVAL; in drm_dp_psr_setup_time()
2170 * drm_dp_start_crc() - start capture of frame CRCs
2189 aux->crc_count = 0; in drm_dp_start_crc()
2190 aux->crtc = crtc; in drm_dp_start_crc()
2191 schedule_work(&aux->crc_work); in drm_dp_start_crc()
2198 * drm_dp_stop_crc() - stop capture of frame CRCs
2216 flush_work(&aux->crc_work); in drm_dp_stop_crc()
2217 aux->crtc = NULL; in drm_dp_stop_crc()
2239 /* LG LP140WF6-SPM1 eDP panel */
2274 if (quirk->is_branch != is_branch) in drm_dp_get_quirks()
2277 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) in drm_dp_get_quirks()
2280 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && in drm_dp_get_quirks()
2281 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) in drm_dp_get_quirks()
2284 quirks |= quirk->quirks; in drm_dp_get_quirks()
2294 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2307 struct drm_dp_dpcd_ident *ident = &desc->ident; in drm_dp_read_desc()
2315 desc->quirks = drm_dp_get_quirks(ident, is_branch); in drm_dp_read_desc()
2317 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); in drm_dp_read_desc()
2319 drm_dbg_kms(aux->drm_dev, in drm_dp_read_desc()
2320 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", in drm_dp_read_desc()
2321 aux->name, is_branch ? "branch" : "sink", in drm_dp_read_desc()
2322 (int)sizeof(ident->oui), ident->oui, dev_id_len, in drm_dp_read_desc()
2323 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, in drm_dp_read_desc()
2324 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); in drm_dp_read_desc()
2331 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2338 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2358 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2376 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2388 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2417 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2433 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2461 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2481 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()
2504 * corrupted values when reading from the 0xF0000- range with a block in drm_dp_read_lttpr_regs()
2525 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2545 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2568 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; in dp_lttpr_common_cap()
2572 * drm_dp_lttpr_count - get the number of detected LTTPRs
2578 * -ERANGE if more than supported number (8) of LTTPRs are detected
2579 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2590 return 8 - ilog2(count); in drm_dp_lttpr_count()
2592 return -ERANGE; in drm_dp_lttpr_count()
2594 return -EINVAL; in drm_dp_lttpr_count()
2600 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2614 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2617 * Returns the maximum lane count supported by all detected LTTPRs.
2628 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2644 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2648 * pre-emphasis level 3.
2660 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2675 data->link_rate = drm_dp_bw_code_to_link_rate(rate); in drm_dp_get_phy_test_pattern()
2680 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_get_phy_test_pattern()
2683 data->enhanced_frame_cap = true; in drm_dp_get_phy_test_pattern()
2685 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); in drm_dp_get_phy_test_pattern()
2689 switch (data->phy_pattern) { in drm_dp_get_phy_test_pattern()
2692 &data->custom80, sizeof(data->custom80)); in drm_dp_get_phy_test_pattern()
2699 &data->hbr2_reset, in drm_dp_get_phy_test_pattern()
2700 sizeof(data->hbr2_reset)); in drm_dp_get_phy_test_pattern()
2710 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2723 test_pattern = data->phy_pattern; in drm_dp_set_phy_test_pattern()
2732 for (i = 0; i < data->num_lanes; i++) { in drm_dp_set_phy_test_pattern()
2826 return "DCI-P3"; in dp_colorimetry_get_name()
2905 vsc->revision, vsc->length); in drm_dp_vsc_sdp_log()
2907 dp_pixelformat_get_name(vsc->pixelformat)); in drm_dp_vsc_sdp_log()
2909 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); in drm_dp_vsc_sdp_log()
2910 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); in drm_dp_vsc_sdp_log()
2912 dp_dynamic_range_get_name(vsc->dynamic_range)); in drm_dp_vsc_sdp_log()
2914 dp_content_type_get_name(vsc->content_type)); in drm_dp_vsc_sdp_log()
2920 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2959 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2981 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3003 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3052 return -EINVAL; in drm_dp_pcon_frl_configure_1()
3064 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3094 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3112 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3126 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", in drm_dp_pcon_frl_enable()
3127 aux->name); in drm_dp_pcon_frl_enable()
3128 return -EINVAL; in drm_dp_pcon_frl_enable()
3140 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3159 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3189 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3201 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; in drm_dp_pcon_hdmi_frl_link_error_count()
3203 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
3222 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", in drm_dp_pcon_hdmi_frl_link_error_count()
3223 aux->name, num_error, i); in drm_dp_pcon_hdmi_frl_link_error_count()
3229 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3239 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_enc_is_dsc_1_2()
3251 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3260 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3261 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3289 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3298 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slice_width()
3305 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3314 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_bpp_incr()
3358 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3377 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3401 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3432 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3434 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3461 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3478 if (!bl->aux_set) in drm_edp_backlight_set_level()
3481 if (bl->lsb_reg_used) { in drm_edp_backlight_set_level()
3490 drm_err(aux->drm_dev, in drm_edp_backlight_set_level()
3492 aux->name, ret); in drm_edp_backlight_set_level()
3493 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_level()
3508 if (!bl->aux_enable) in drm_edp_backlight_set_enable()
3513 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3514 aux->name, ret); in drm_edp_backlight_set_enable()
3515 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3524 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3525 aux->name, ret); in drm_edp_backlight_set_enable()
3526 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3533 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3543 * that the driver handle enabling/disabling the panel through implementation-specific means using
3545 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3556 if (bl->aux_set) in drm_edp_backlight_enable()
3561 if (bl->pwmgen_bit_count) { in drm_edp_backlight_enable()
3562 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); in drm_edp_backlight_enable()
3564 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_enable()
3565 aux->name, ret); in drm_edp_backlight_enable()
3568 if (bl->pwm_freq_pre_divider) { in drm_edp_backlight_enable()
3569 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); in drm_edp_backlight_enable()
3571 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_enable()
3573 aux->name, ret); in drm_edp_backlight_enable()
3580 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", in drm_edp_backlight_enable()
3581 aux->name, ret); in drm_edp_backlight_enable()
3582 return ret < 0 ? ret : -EIO; in drm_edp_backlight_enable()
3597 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3604 * that the driver handle enabling/disabling the panel through implementation-specific means using
3606 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3609 * Returns: %0 on success or no-op, negative error code on failure.
3631 if (!bl->aux_set) in drm_edp_backlight_probe_max()
3636 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", in drm_edp_backlight_probe_max()
3637 aux->name, ret); in drm_edp_backlight_probe_max()
3638 return -ENODEV; in drm_edp_backlight_probe_max()
3642 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3649 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the in drm_edp_backlight_probe_max()
3651 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the in drm_edp_backlight_probe_max()
3663 * - Pn is in the range of Pn_min and Pn_max in drm_edp_backlight_probe_max()
3664 * - F is in the range of 1 and 255 in drm_edp_backlight_probe_max()
3665 * - FxP is within 25% of desired value. in drm_edp_backlight_probe_max()
3670 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", in drm_edp_backlight_probe_max()
3671 aux->name, ret); in drm_edp_backlight_probe_max()
3676 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", in drm_edp_backlight_probe_max()
3677 aux->name, ret); in drm_edp_backlight_probe_max()
3687 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_probe_max()
3689 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3693 for (pn = pn_max; pn >= pn_min; pn--) { in drm_edp_backlight_probe_max()
3702 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_probe_max()
3703 aux->name, ret); in drm_edp_backlight_probe_max()
3706 bl->pwmgen_bit_count = pn; in drm_edp_backlight_probe_max()
3707 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3710 bl->pwm_freq_pre_divider = f; in drm_edp_backlight_probe_max()
3711 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", in drm_edp_backlight_probe_max()
3712 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3728 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", in drm_edp_backlight_probe_state()
3729 aux->name, ret); in drm_edp_backlight_probe_state()
3730 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3734 if (!bl->aux_set) in drm_edp_backlight_probe_state()
3738 int size = 1 + bl->lsb_reg_used; in drm_edp_backlight_probe_state()
3742 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", in drm_edp_backlight_probe_state()
3743 aux->name, ret); in drm_edp_backlight_probe_state()
3744 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3747 if (bl->lsb_reg_used) in drm_edp_backlight_probe_state()
3757 return bl->max; in drm_edp_backlight_probe_state()
3761 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3773 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3786 bl->aux_enable = true; in drm_edp_backlight_init()
3788 bl->aux_set = true; in drm_edp_backlight_init()
3790 bl->lsb_reg_used = true; in drm_edp_backlight_init()
3793 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { in drm_edp_backlight_init()
3794 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3796 aux->name); in drm_edp_backlight_init()
3797 return -EINVAL; in drm_edp_backlight_init()
3809 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3811 aux->name, bl->aux_set, bl->aux_enable, *current_mode); in drm_edp_backlight_init()
3812 if (bl->aux_set) { in drm_edp_backlight_init()
3813 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3815 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, in drm_edp_backlight_init()
3816 bl->lsb_reg_used); in drm_edp_backlight_init()
3833 if (!bl->enabled) { in dp_aux_backlight_update_status()
3834 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
3835 bl->enabled = true; in dp_aux_backlight_update_status()
3838 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
3840 if (bl->enabled) { in dp_aux_backlight_update_status()
3841 drm_edp_backlight_disable(bl->aux, &bl->info); in dp_aux_backlight_update_status()
3842 bl->enabled = false; in dp_aux_backlight_update_status()
3854 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3886 if (!panel || !panel->dev || !aux) in drm_panel_dp_aux_backlight()
3887 return -EINVAL; in drm_panel_dp_aux_backlight()
3895 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); in drm_panel_dp_aux_backlight()
3899 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); in drm_panel_dp_aux_backlight()
3901 return -ENOMEM; in drm_panel_dp_aux_backlight()
3903 bl->aux = aux; in drm_panel_dp_aux_backlight()
3905 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, in drm_panel_dp_aux_backlight()
3912 props.max_brightness = bl->info.max; in drm_panel_dp_aux_backlight()
3914 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", in drm_panel_dp_aux_backlight()
3915 panel->dev, bl, in drm_panel_dp_aux_backlight()
3917 if (IS_ERR(bl->base)) in drm_panel_dp_aux_backlight()
3918 return PTR_ERR(bl->base); in drm_panel_dp_aux_backlight()
3920 backlight_disable(bl->base); in drm_panel_dp_aux_backlight()
3922 panel->backlight = bl->base; in drm_panel_dp_aux_backlight()
3952 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
3953 * @lane_count: DP link lane count
3961 * - @lane_count
3962 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
3963 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
3964 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
3965 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
3967 * - @hactive timing
3968 * - @bpp_x16 color depth
3969 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
3996 * After each 250 data symbols on 2-4 lanes: in drm_dp_bw_overhead()
3998 * After each 2 x 250 data symbols on 1 lane: in drm_dp_bw_overhead()
4000 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: in drm_dp_bw_overhead()
4034 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4039 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4045 * Returns the efficiency in the 100%/coding-overhead% ratio in