Lines Matching +full:dp +full:- +full:aux +full:- +full:bus
58 struct drm_dp_aux *aux; member
64 * DOC: dp helpers
67 * levels to deal with Display Port sink devices and related things like DP aux
68 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
72 /* Helpers for DP link training */
75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
149 /* DP 2.0 128b/132b */
163 /* DP 2.0 errata for 128b/132b */
183 /* DP 2.0 errata for 128b/132b */
199 /* DP 2.0 errata for 128b/132b */
208 /* DP 2.0 errata for 128b/132b */
217 /* DP 2.0 errata for 128b/132b */
226 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) in __8b10b_clock_recovery_delay_us() argument
229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
230 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
238 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) in __8b10b_channel_eq_delay_us() argument
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
242 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
250 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) in __128b132b_channel_eq_delay_us() argument
254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
255 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
277 * - Clock recovery vs. channel equalization
278 * - DPRX vs. LTTPR
279 * - 128b/132b vs. 8b/10b
280 * - DPCD rev 1.3 vs. later
284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay() argument
287 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); in __read_delay()
328 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { in __read_delay()
329 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", in __read_delay()
330 aux->name); in __read_delay()
336 return parse(aux, rd_interval & mask); in __read_delay()
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay() argument
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay() argument
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
353 /* Per DP 2.0 Errata */
354 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) in drm_dp_128b132b_read_aux_rd_interval() argument
359 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { in drm_dp_128b132b_read_aux_rd_interval()
360 drm_err(aux->drm_dev, "%s: failed rd interval read\n", in drm_dp_128b132b_read_aux_rd_interval()
361 aux->name); in drm_dp_128b132b_read_aux_rd_interval()
373 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, in drm_dp_link_train_clock_recovery_delay() argument
383 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); in drm_dp_link_train_clock_recovery_delay()
389 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, in __drm_dp_link_train_channel_eq_delay() argument
392 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); in __drm_dp_link_train_channel_eq_delay()
397 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, in drm_dp_link_train_channel_eq_delay() argument
400 __drm_dp_link_train_channel_eq_delay(aux, in drm_dp_link_train_channel_eq_delay()
407 * drm_dp_phy_name() - Get the name of the given DP PHY
408 * @dp_phy: The DP PHY identifier
410 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
411 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
412 * non-NULL and valid.
414 * Returns: Name of the DP PHY.
432 return "<INVALID DP PHY>"; in drm_dp_phy_name()
446 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; in dp_lttpr_phy_cap()
449 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, in drm_dp_lttpr_link_train_channel_eq_delay() argument
456 __drm_dp_link_train_channel_eq_delay(aux, interval); in drm_dp_lttpr_link_train_channel_eq_delay()
495 drm_dp_dump_access(const struct drm_dp_aux *aux, in drm_dp_dump_access() argument
498 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; in drm_dp_dump_access()
501 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", in drm_dp_dump_access()
502 aux->name, offset, arrow, ret, min(ret, 20), buffer); in drm_dp_dump_access()
504 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", in drm_dp_dump_access()
505 aux->name, offset, arrow, ret); in drm_dp_dump_access()
509 * DOC: dp helpers
511 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
512 * independent access to AUX functionality. Drivers can take advantage of
515 * Transactions are described using a hardware-independent drm_dp_aux_msg
517 * Both native and I2C-over-AUX transactions are supported.
520 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, in drm_dp_dpcd_access() argument
533 mutex_lock(&aux->hw_mutex); in drm_dp_dpcd_access()
538 * aux i2c transactions but real world devices this wasn't in drm_dp_dpcd_access()
542 if (ret != 0 && ret != -ETIMEDOUT) { in drm_dp_dpcd_access()
547 ret = aux->transfer(aux, &msg); in drm_dp_dpcd_access()
554 ret = -EPROTO; in drm_dp_dpcd_access()
556 ret = -EIO; in drm_dp_dpcd_access()
568 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", in drm_dp_dpcd_access()
569 aux->name, err); in drm_dp_dpcd_access()
573 mutex_unlock(&aux->hw_mutex); in drm_dp_dpcd_access()
578 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
579 * @aux: DisplayPort AUX channel (SST)
583 * be used to trigger some side-effect the read access has, like waking up the
584 * sink, without the need for the read-out value.
588 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) in drm_dp_dpcd_probe() argument
593 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); in drm_dp_dpcd_probe()
596 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); in drm_dp_dpcd_probe()
603 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
604 * @aux: DisplayPort AUX channel (SST or MST)
610 * code on failure. -EIO is returned if the request was NAKed by the sink or
612 * function returns -EPROTO. Errors from the underlying AUX channel transfer
613 * function, with the exception of -EBUSY (which causes the transaction to
616 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, in drm_dp_dpcd_read() argument
626 * gets woken up and subsequently re-enters power save mode. in drm_dp_dpcd_read()
633 if (!aux->is_remote) { in drm_dp_dpcd_read()
634 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); in drm_dp_dpcd_read()
639 if (aux->is_remote) in drm_dp_dpcd_read()
640 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); in drm_dp_dpcd_read()
642 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, in drm_dp_dpcd_read()
645 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); in drm_dp_dpcd_read()
651 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
652 * @aux: DisplayPort AUX channel (SST or MST)
658 * code on failure. -EIO is returned if the request was NAKed by the sink or
660 * function returns -EPROTO. Errors from the underlying AUX channel transfer
661 * function, with the exception of -EBUSY (which causes the transaction to
664 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, in drm_dp_dpcd_write() argument
669 if (aux->is_remote) in drm_dp_dpcd_write()
670 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); in drm_dp_dpcd_write()
672 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, in drm_dp_dpcd_write()
675 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); in drm_dp_dpcd_write()
681 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
682 * @aux: DisplayPort AUX channel
688 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, in drm_dp_dpcd_read_link_status() argument
691 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, in drm_dp_dpcd_read_link_status()
697 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
698 * @aux: DisplayPort AUX channel
699 * @dp_phy: the DP PHY to get the link status for
702 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
709 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, in drm_dp_dpcd_read_phy_link_status() argument
716 ret = drm_dp_dpcd_read(aux, in drm_dp_dpcd_read_phy_link_status()
729 ret = drm_dp_dpcd_read(aux, in drm_dp_dpcd_read_phy_link_status()
732 DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
737 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
740 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], in drm_dp_dpcd_read_phy_link_status()
741 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], in drm_dp_dpcd_read_phy_link_status()
742 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); in drm_dp_dpcd_read_phy_link_status()
743 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; in drm_dp_dpcd_read_phy_link_status()
754 return edid && edid->revision >= 4 && in is_edid_digital_input_dp()
755 edid->input & DRM_EDID_INPUT_DIGITAL && in is_edid_digital_input_dp()
756 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; in is_edid_digital_input_dp()
760 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
782 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
817 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
818 * @aux: DisplayPort AUX channel
824 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, in drm_dp_send_real_edid_checksum() argument
829 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, in drm_dp_send_real_edid_checksum()
831 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
832 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
837 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { in drm_dp_send_real_edid_checksum()
838 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
839 aux->name, DP_TEST_REQUEST); in drm_dp_send_real_edid_checksum()
845 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", in drm_dp_send_real_edid_checksum()
846 aux->name); in drm_dp_send_real_edid_checksum()
850 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, in drm_dp_send_real_edid_checksum()
852 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
853 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
858 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, in drm_dp_send_real_edid_checksum()
860 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
861 aux->name, DP_TEST_EDID_CHECKSUM); in drm_dp_send_real_edid_checksum()
866 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { in drm_dp_send_real_edid_checksum()
867 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
868 aux->name, DP_TEST_RESPONSE); in drm_dp_send_real_edid_checksum()
886 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, in drm_dp_read_extended_dpcd_caps() argument
903 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, in drm_dp_read_extended_dpcd_caps()
908 return -EIO; in drm_dp_read_extended_dpcd_caps()
911 drm_dbg_kms(aux->drm_dev, in drm_dp_read_extended_dpcd_caps()
913 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
920 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
928 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
930 * @aux: DisplayPort AUX channel
933 * Attempts to read the base DPCD caps for @aux. Additionally, this function
940 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, in drm_dp_read_dpcd_caps() argument
945 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_read_dpcd_caps()
949 return -EIO; in drm_dp_read_dpcd_caps()
951 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); in drm_dp_read_dpcd_caps()
955 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
962 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
963 * @aux: DisplayPort AUX channel
974 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, in drm_dp_read_downstream_info() argument
988 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since in drm_dp_read_downstream_info()
998 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); in drm_dp_read_downstream_info()
1002 return -EIO; in drm_dp_read_downstream_info()
1004 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); in drm_dp_read_downstream_info()
1011 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1039 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1069 * DP dual mode adapter's max TMDS clock. in drm_dp_downstream_max_tmds_clock()
1072 * may not fordward that the DP dual mode i2c in drm_dp_downstream_max_tmds_clock()
1104 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1147 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1204 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1205 * YCbCr 4:2:0 pass-through capability
1235 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1236 * YCbCr 4:4:4->4:2:0 conversion capability
1264 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1265 * RGB->YCbCr conversion capability
1270 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1296 * drm_dp_downstream_mode() - return a mode for downstream facing port
1351 * drm_dp_downstream_id() - identify branch device
1352 * @aux: DisplayPort AUX channel
1357 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) in drm_dp_downstream_id() argument
1359 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); in drm_dp_downstream_id()
1364 * drm_dp_downstream_debug() - debug DP branch devices
1369 * @aux: DisplayPort AUX channel
1376 struct drm_dp_aux *aux) in drm_dp_downstream_debug() argument
1411 seq_puts(m, "\t\tType: DP++\n"); in drm_dp_downstream_debug()
1421 drm_dp_downstream_id(aux, id); in drm_dp_downstream_debug()
1424 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); in drm_dp_downstream_debug()
1429 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); in drm_dp_downstream_debug()
1455 * drm_dp_subconnector_type() - get DP branch device type
1466 /* DP 1.0 approach */ in drm_dp_subconnector_type()
1473 /* Can be HDMI or DVI-D, DVI-D is a safer option */ in drm_dp_subconnector_type()
1476 /* Can be VGA or DVI-A, VGA is more popular */ in drm_dp_subconnector_type()
1507 * drm_dp_set_subconnector_property - set subconnector for DP connector
1524 drm_object_property_set_value(&connector->base, in drm_dp_set_subconnector_property()
1525 connector->dev->mode_config.dp_subconnector_property, in drm_dp_set_subconnector_property()
1531 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1535 * @desc: A cached copy of the connector's DP descriptor
1539 * Returns: %True if the (e)DP connector has a valid sink count that should
1547 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && in drm_dp_read_sink_count_cap()
1555 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1556 * @aux: The DP AUX channel to use
1560 * Returns: The current sink count reported by @aux, or a negative error code
1563 int drm_dp_read_sink_count(struct drm_dp_aux *aux) in drm_dp_read_sink_count() argument
1568 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); in drm_dp_read_sink_count()
1572 return -EIO; in drm_dp_read_sink_count()
1579 * I2C-over-AUX implementation
1597 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { in drm_dp_i2c_msg_write_status_update()
1598 msg->request &= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_write_status_update()
1599 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; in drm_dp_i2c_msg_write_status_update()
1612 * Calculate the duration of the AUX request/reply in usec. Gives the
1620 if ((msg->request & DP_AUX_I2C_READ) == 0) in drm_dp_aux_req_duration()
1621 len += msg->size * 8; in drm_dp_aux_req_duration()
1635 if (msg->request & DP_AUX_I2C_READ) in drm_dp_aux_reply_duration()
1636 len += msg->size * 8; in drm_dp_aux_reply_duration()
1648 * the i2c bus speed is as specified. Gives the "worst"
1657 /* AUX bitrate is 1MHz, i2c bitrate as specified */ in drm_dp_i2c_msg_duration()
1659 msg->size * I2C_DATA_LEN + in drm_dp_i2c_msg_duration()
1666 * i2c and AUX transfers.
1685 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1688 * Transfer a single I2C-over-AUX message and handle various error conditions,
1695 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) in drm_dp_i2c_do_msg() argument
1700 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device in drm_dp_i2c_do_msg()
1702 * before giving up the AUX transaction. in drm_dp_i2c_do_msg()
1704 * We also try to account for the i2c bus speed. in drm_dp_i2c_do_msg()
1709 ret = aux->transfer(aux, msg); in drm_dp_i2c_do_msg()
1711 if (ret == -EBUSY) in drm_dp_i2c_do_msg()
1717 * communicate with a non-existent DisplayPort device). in drm_dp_i2c_do_msg()
1720 if (ret == -ETIMEDOUT) in drm_dp_i2c_do_msg()
1721 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", in drm_dp_i2c_do_msg()
1722 aux->name); in drm_dp_i2c_do_msg()
1724 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", in drm_dp_i2c_do_msg()
1725 aux->name, ret); in drm_dp_i2c_do_msg()
1730 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { in drm_dp_i2c_do_msg()
1733 * For I2C-over-AUX transactions this isn't enough, we in drm_dp_i2c_do_msg()
1739 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1740 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1741 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1744 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); in drm_dp_i2c_do_msg()
1748 * more careful with DP-to-legacy adapters where a in drm_dp_i2c_do_msg()
1752 * safe for all use-cases. in drm_dp_i2c_do_msg()
1758 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", in drm_dp_i2c_do_msg()
1759 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1760 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1763 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { in drm_dp_i2c_do_msg()
1769 if (ret != msg->size) in drm_dp_i2c_do_msg()
1774 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1775 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1776 aux->i2c_nack_count++; in drm_dp_i2c_do_msg()
1777 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1780 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); in drm_dp_i2c_do_msg()
1781 /* DP Compliance Test 4.2.2.5 Requirement: in drm_dp_i2c_do_msg()
1785 aux->i2c_defer_count++; in drm_dp_i2c_do_msg()
1794 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", in drm_dp_i2c_do_msg()
1795 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1796 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1800 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); in drm_dp_i2c_do_msg()
1801 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1807 msg->request = (i2c_msg->flags & I2C_M_RD) ? in drm_dp_i2c_msg_set_request()
1809 if (!(i2c_msg->flags & I2C_M_STOP)) in drm_dp_i2c_msg_set_request()
1810 msg->request |= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_set_request()
1818 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) in drm_dp_i2c_drain_msg() argument
1820 int err, ret = orig_msg->size; in drm_dp_i2c_drain_msg()
1824 err = drm_dp_i2c_do_msg(aux, &msg); in drm_dp_i2c_drain_msg()
1826 return err == 0 ? -EPROTO : err; in drm_dp_i2c_drain_msg()
1829 drm_dbg_kms(aux->drm_dev, in drm_dp_i2c_drain_msg()
1831 aux->name, msg.size, err); in drm_dp_i2c_drain_msg()
1835 msg.size -= err; in drm_dp_i2c_drain_msg()
1843 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1850 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1855 struct drm_dp_aux *aux = adapter->algo_data; in drm_dp_i2c_xfer() local
1874 err = drm_dp_i2c_do_msg(aux, &msg); in drm_dp_i2c_xfer()
1891 msg.size = min(transfer_size, msgs[i].len - j); in drm_dp_i2c_xfer()
1893 err = drm_dp_i2c_drain_msg(aux, &msg); in drm_dp_i2c_xfer()
1917 (void)drm_dp_i2c_do_msg(aux, &msg); in drm_dp_i2c_xfer()
1934 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); in lock_bus()
1939 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); in trylock_bus()
1944 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); in unlock_bus()
1953 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) in drm_dp_aux_get_crc() argument
1958 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); in drm_dp_aux_get_crc()
1964 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); in drm_dp_aux_get_crc()
1969 if (count == aux->crc_count) in drm_dp_aux_get_crc()
1970 return -EAGAIN; /* No CRC yet */ in drm_dp_aux_get_crc()
1972 aux->crc_count = count; in drm_dp_aux_get_crc()
1978 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); in drm_dp_aux_get_crc()
1987 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, in drm_dp_aux_crc_work() local
1994 if (WARN_ON(!aux->crtc)) in drm_dp_aux_crc_work()
1997 crtc = aux->crtc; in drm_dp_aux_crc_work()
1998 while (crtc->crc.opened) { in drm_dp_aux_crc_work()
2000 if (!crtc->crc.opened) in drm_dp_aux_crc_work()
2003 ret = drm_dp_aux_get_crc(aux, crc_bytes); in drm_dp_aux_crc_work()
2004 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2006 ret = drm_dp_aux_get_crc(aux, crc_bytes); in drm_dp_aux_crc_work()
2009 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2010 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", in drm_dp_aux_crc_work()
2011 aux->name, ret); in drm_dp_aux_crc_work()
2014 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); in drm_dp_aux_crc_work()
2026 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2027 * @aux: DisplayPort AUX channel
2029 * Used for remote aux channel in general. Merely initialize the crc work
2032 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) in drm_dp_remote_aux_init() argument
2034 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_remote_aux_init()
2039 * drm_dp_aux_init() - minimally initialise an aux channel
2040 * @aux: DisplayPort AUX channel
2044 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2046 * has been registered to allow userspace access to the auxiliary DP channel.
2048 * early as possible so that the &drm_device that corresponds to the AUX adapter
2049 * may be mentioned in debugging output from the DRM DP helpers.
2051 * For devices which use a separate platform device for their AUX adapters, this
2055 void drm_dp_aux_init(struct drm_dp_aux *aux) in drm_dp_aux_init() argument
2057 mutex_init(&aux->hw_mutex); in drm_dp_aux_init()
2058 mutex_init(&aux->cec.lock); in drm_dp_aux_init()
2059 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_aux_init()
2061 aux->ddc.algo = &drm_dp_i2c_algo; in drm_dp_aux_init()
2062 aux->ddc.algo_data = aux; in drm_dp_aux_init()
2063 aux->ddc.retries = 3; in drm_dp_aux_init()
2065 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; in drm_dp_aux_init()
2070 * drm_dp_aux_register() - initialise and register aux channel
2071 * @aux: DisplayPort AUX channel
2074 * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2075 * initialized. For devices which are grandparents of their AUX channels,
2077 * corresponds to @aux. For these devices, it's advised to call
2083 * For devices where the AUX channel is a device that exists independently of
2088 * with the AUX channel (e.g. on bridge detach).
2090 * Drivers which need to use the aux channel before either of the two points
2091 * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2096 int drm_dp_aux_register(struct drm_dp_aux *aux) in drm_dp_aux_register() argument
2100 WARN_ON_ONCE(!aux->drm_dev); in drm_dp_aux_register()
2102 if (!aux->ddc.algo) in drm_dp_aux_register()
2103 drm_dp_aux_init(aux); in drm_dp_aux_register()
2105 aux->ddc.owner = THIS_MODULE; in drm_dp_aux_register()
2106 aux->ddc.dev.parent = aux->dev; in drm_dp_aux_register()
2108 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), in drm_dp_aux_register()
2109 sizeof(aux->ddc.name)); in drm_dp_aux_register()
2111 ret = drm_dp_aux_register_devnode(aux); in drm_dp_aux_register()
2115 ret = i2c_add_adapter(&aux->ddc); in drm_dp_aux_register()
2117 drm_dp_aux_unregister_devnode(aux); in drm_dp_aux_register()
2126 * drm_dp_aux_unregister() - unregister an AUX adapter
2127 * @aux: DisplayPort AUX channel
2129 void drm_dp_aux_unregister(struct drm_dp_aux *aux) in drm_dp_aux_unregister() argument
2131 drm_dp_aux_unregister_devnode(aux); in drm_dp_aux_unregister()
2132 i2c_del_adapter(&aux->ddc); in drm_dp_aux_unregister()
2139 * drm_dp_psr_setup_time() - PSR setup in time usec
2161 return -EINVAL; in drm_dp_psr_setup_time()
2170 * drm_dp_start_crc() - start capture of frame CRCs
2171 * @aux: DisplayPort AUX channel
2176 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) in drm_dp_start_crc() argument
2181 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); in drm_dp_start_crc()
2185 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); in drm_dp_start_crc()
2189 aux->crc_count = 0; in drm_dp_start_crc()
2190 aux->crtc = crtc; in drm_dp_start_crc()
2191 schedule_work(&aux->crc_work); in drm_dp_start_crc()
2198 * drm_dp_stop_crc() - stop capture of frame CRCs
2199 * @aux: DisplayPort AUX channel
2203 int drm_dp_stop_crc(struct drm_dp_aux *aux) in drm_dp_stop_crc() argument
2208 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); in drm_dp_stop_crc()
2212 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); in drm_dp_stop_crc()
2216 flush_work(&aux->crc_work); in drm_dp_stop_crc()
2217 aux->crtc = NULL; in drm_dp_stop_crc()
2239 /* LG LP140WF6-SPM1 eDP panel */
2274 if (quirk->is_branch != is_branch) in drm_dp_get_quirks()
2277 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) in drm_dp_get_quirks()
2280 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && in drm_dp_get_quirks()
2281 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) in drm_dp_get_quirks()
2284 quirks |= quirk->quirks; in drm_dp_get_quirks()
2294 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2295 * @aux: DisplayPort AUX channel
2304 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, in drm_dp_read_desc() argument
2307 struct drm_dp_dpcd_ident *ident = &desc->ident; in drm_dp_read_desc()
2311 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); in drm_dp_read_desc()
2315 desc->quirks = drm_dp_get_quirks(ident, is_branch); in drm_dp_read_desc()
2317 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); in drm_dp_read_desc()
2319 drm_dbg_kms(aux->drm_dev, in drm_dp_read_desc()
2320 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", in drm_dp_read_desc()
2321 aux->name, is_branch ? "branch" : "sink", in drm_dp_read_desc()
2322 (int)sizeof(ident->oui), ident->oui, dev_id_len, in drm_dp_read_desc()
2323 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf, in drm_dp_read_desc()
2324 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks); in drm_dp_read_desc()
2331 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2334 * Returns the bpp precision supported by the DP sink.
2338 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2358 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2361 * @is_edp: true if its eDP, false for DP
2376 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2387 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ in drm_dp_dsc_sink_max_slice_count()
2388 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2417 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2433 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2461 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2481 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()
2491 /* A DP DSC Sink device shall support 8 bpc. */ in drm_dp_dsc_sink_supported_input_bpcs()
2498 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, in drm_dp_read_lttpr_regs() argument
2504 * corrupted values when reading from the 0xF0000- range with a block in drm_dp_read_lttpr_regs()
2512 ret = drm_dp_dpcd_read(aux, in drm_dp_read_lttpr_regs()
2525 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2526 * @aux: DisplayPort AUX channel
2534 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, in drm_dp_read_lttpr_common_caps() argument
2538 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_common_caps()
2545 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2546 * @aux: DisplayPort AUX channel
2555 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, in drm_dp_read_lttpr_phy_caps() argument
2560 return drm_dp_read_lttpr_regs(aux, dpcd, in drm_dp_read_lttpr_phy_caps()
2568 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; in dp_lttpr_common_cap()
2572 * drm_dp_lttpr_count - get the number of detected LTTPRs
2578 * -ERANGE if more than supported number (8) of LTTPRs are detected
2579 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2590 return 8 - ilog2(count); in drm_dp_lttpr_count()
2592 return -ERANGE; in drm_dp_lttpr_count()
2594 return -EINVAL; in drm_dp_lttpr_count()
2600 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2614 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2628 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2644 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2648 * pre-emphasis level 3.
2660 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2661 * @aux: DisplayPort AUX channel
2662 * @data: DP phy compliance test parameters.
2666 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, in drm_dp_get_phy_test_pattern() argument
2672 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); in drm_dp_get_phy_test_pattern()
2675 data->link_rate = drm_dp_bw_code_to_link_rate(rate); in drm_dp_get_phy_test_pattern()
2677 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); in drm_dp_get_phy_test_pattern()
2680 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_get_phy_test_pattern()
2683 data->enhanced_frame_cap = true; in drm_dp_get_phy_test_pattern()
2685 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); in drm_dp_get_phy_test_pattern()
2689 switch (data->phy_pattern) { in drm_dp_get_phy_test_pattern()
2691 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, in drm_dp_get_phy_test_pattern()
2692 &data->custom80, sizeof(data->custom80)); in drm_dp_get_phy_test_pattern()
2698 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, in drm_dp_get_phy_test_pattern()
2699 &data->hbr2_reset, in drm_dp_get_phy_test_pattern()
2700 sizeof(data->hbr2_reset)); in drm_dp_get_phy_test_pattern()
2710 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2711 * @aux: DisplayPort AUX channel
2712 * @data: DP phy compliance test parameters.
2713 * @dp_rev: DP revision to use for compliance testing
2717 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, in drm_dp_set_phy_test_pattern() argument
2723 test_pattern = data->phy_pattern; in drm_dp_set_phy_test_pattern()
2727 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, in drm_dp_set_phy_test_pattern()
2732 for (i = 0; i < data->num_lanes; i++) { in drm_dp_set_phy_test_pattern()
2733 err = drm_dp_dpcd_writeb(aux, in drm_dp_set_phy_test_pattern()
2826 return "DCI-P3"; in dp_colorimetry_get_name()
2904 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", in drm_dp_vsc_sdp_log()
2905 vsc->revision, vsc->length); in drm_dp_vsc_sdp_log()
2907 dp_pixelformat_get_name(vsc->pixelformat)); in drm_dp_vsc_sdp_log()
2909 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); in drm_dp_vsc_sdp_log()
2910 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); in drm_dp_vsc_sdp_log()
2912 dp_dynamic_range_get_name(vsc->dynamic_range)); in drm_dp_vsc_sdp_log()
2914 dp_content_type_get_name(vsc->content_type)); in drm_dp_vsc_sdp_log()
2920 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2959 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2960 * @aux: DisplayPort AUX channel
2965 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) in drm_dp_pcon_frl_prepare() argument
2974 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in drm_dp_pcon_frl_prepare()
2981 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2982 * @aux: DisplayPort AUX channel
2986 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) in drm_dp_pcon_is_frl_ready() argument
2991 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); in drm_dp_pcon_is_frl_ready()
3003 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3004 * @aux: DisplayPort AUX channel
3008 * DP Link training. In Sequential mode, the FRL link bring up is done prior to
3009 * the DP Link training.
3014 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, in drm_dp_pcon_frl_configure_1() argument
3020 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); in drm_dp_pcon_frl_configure_1()
3052 return -EINVAL; in drm_dp_pcon_frl_configure_1()
3055 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in drm_dp_pcon_frl_configure_1()
3064 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3065 * @aux: DisplayPort AUX channel
3074 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, in drm_dp_pcon_frl_configure_2() argument
3085 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); in drm_dp_pcon_frl_configure_2()
3094 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3095 * @aux: DisplayPort AUX channel
3099 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) in drm_dp_pcon_reset_frl_config() argument
3103 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); in drm_dp_pcon_reset_frl_config()
3112 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3113 * @aux: DisplayPort AUX channel
3117 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) in drm_dp_pcon_frl_enable() argument
3122 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); in drm_dp_pcon_frl_enable()
3126 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", in drm_dp_pcon_frl_enable()
3127 aux->name); in drm_dp_pcon_frl_enable()
3128 return -EINVAL; in drm_dp_pcon_frl_enable()
3131 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in drm_dp_pcon_frl_enable()
3140 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3141 * @aux: DisplayPort AUX channel
3145 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) in drm_dp_pcon_hdmi_link_active() argument
3150 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); in drm_dp_pcon_hdmi_link_active()
3159 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3160 * @aux: DisplayPort AUX channel
3169 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) in drm_dp_pcon_hdmi_link_mode() argument
3175 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); in drm_dp_pcon_hdmi_link_mode()
3189 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3191 * @aux: DisplayPort AUX channel
3196 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, in drm_dp_pcon_hdmi_frl_link_error_count() argument
3201 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; in drm_dp_pcon_hdmi_frl_link_error_count()
3203 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
3204 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) in drm_dp_pcon_hdmi_frl_link_error_count()
3222 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", in drm_dp_pcon_hdmi_frl_link_error_count()
3223 aux->name, num_error, i); in drm_dp_pcon_hdmi_frl_link_error_count()
3229 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3239 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_enc_is_dsc_1_2()
3251 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3260 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3261 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3289 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3298 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slice_width()
3305 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3314 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_bpp_incr()
3334 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) in drm_dp_pcon_configure_dsc_enc() argument
3339 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); in drm_dp_pcon_configure_dsc_enc()
3350 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); in drm_dp_pcon_configure_dsc_enc()
3358 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3360 * @aux: DisplayPort AUX channel
3364 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) in drm_dp_pcon_pps_default() argument
3368 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); in drm_dp_pcon_pps_default()
3377 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3379 * @aux: DisplayPort AUX channel
3384 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) in drm_dp_pcon_pps_override_buf() argument
3388 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); in drm_dp_pcon_pps_override_buf()
3392 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); in drm_dp_pcon_pps_override_buf()
3401 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3403 * @aux: DisplayPort AUX channel
3409 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) in drm_dp_pcon_pps_override_param() argument
3413 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); in drm_dp_pcon_pps_override_param()
3416 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); in drm_dp_pcon_pps_override_param()
3419 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); in drm_dp_pcon_pps_override_param()
3423 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); in drm_dp_pcon_pps_override_param()
3432 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3433 * @aux: displayPort AUX channel
3434 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3438 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) in drm_dp_pcon_convert_rgb_to_ycbcr() argument
3443 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); in drm_dp_pcon_convert_rgb_to_ycbcr()
3452 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); in drm_dp_pcon_convert_rgb_to_ycbcr()
3461 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3462 * @aux: The DP AUX channel to use
3471 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, in drm_edp_backlight_set_level() argument
3478 if (!bl->aux_set) in drm_edp_backlight_set_level()
3481 if (bl->lsb_reg_used) { in drm_edp_backlight_set_level()
3488 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); in drm_edp_backlight_set_level()
3490 drm_err(aux->drm_dev, in drm_edp_backlight_set_level()
3491 "%s: Failed to write aux backlight level: %d\n", in drm_edp_backlight_set_level()
3492 aux->name, ret); in drm_edp_backlight_set_level()
3493 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_level()
3501 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, in drm_edp_backlight_set_enable() argument
3508 if (!bl->aux_enable) in drm_edp_backlight_set_enable()
3511 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); in drm_edp_backlight_set_enable()
3513 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3514 aux->name, ret); in drm_edp_backlight_set_enable()
3515 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3522 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); in drm_edp_backlight_set_enable()
3524 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3525 aux->name, ret); in drm_edp_backlight_set_enable()
3526 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3533 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3534 * @aux: The DP AUX channel to use
3536 * @level: The initial backlight level to set via AUX, if there is one
3543 * that the driver handle enabling/disabling the panel through implementation-specific means using
3545 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3550 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, in drm_edp_backlight_enable() argument
3556 if (bl->aux_set) in drm_edp_backlight_enable()
3561 if (bl->pwmgen_bit_count) { in drm_edp_backlight_enable()
3562 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); in drm_edp_backlight_enable()
3564 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_enable()
3565 aux->name, ret); in drm_edp_backlight_enable()
3568 if (bl->pwm_freq_pre_divider) { in drm_edp_backlight_enable()
3569 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); in drm_edp_backlight_enable()
3571 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_enable()
3572 "%s: Failed to write aux backlight frequency: %d\n", in drm_edp_backlight_enable()
3573 aux->name, ret); in drm_edp_backlight_enable()
3578 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); in drm_edp_backlight_enable()
3580 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", in drm_edp_backlight_enable()
3581 aux->name, ret); in drm_edp_backlight_enable()
3582 return ret < 0 ? ret : -EIO; in drm_edp_backlight_enable()
3585 ret = drm_edp_backlight_set_level(aux, bl, level); in drm_edp_backlight_enable()
3588 ret = drm_edp_backlight_set_enable(aux, bl, true); in drm_edp_backlight_enable()
3597 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3598 * @aux: The DP AUX channel to use
3601 * This function handles disabling DPCD backlight controls on a panel over AUX.
3604 * that the driver handle enabling/disabling the panel through implementation-specific means using
3606 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3609 * Returns: %0 on success or no-op, negative error code on failure.
3611 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) in drm_edp_backlight_disable() argument
3615 ret = drm_edp_backlight_set_enable(aux, bl, false); in drm_edp_backlight_disable()
3624 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, in drm_edp_backlight_probe_max() argument
3631 if (!bl->aux_set) in drm_edp_backlight_probe_max()
3634 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); in drm_edp_backlight_probe_max()
3636 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", in drm_edp_backlight_probe_max()
3637 aux->name, ret); in drm_edp_backlight_probe_max()
3638 return -ENODEV; in drm_edp_backlight_probe_max()
3642 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3649 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the in drm_edp_backlight_probe_max()
3651 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the in drm_edp_backlight_probe_max()
3663 * - Pn is in the range of Pn_min and Pn_max in drm_edp_backlight_probe_max()
3664 * - F is in the range of 1 and 255 in drm_edp_backlight_probe_max()
3665 * - FxP is within 25% of desired value. in drm_edp_backlight_probe_max()
3668 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); in drm_edp_backlight_probe_max()
3670 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", in drm_edp_backlight_probe_max()
3671 aux->name, ret); in drm_edp_backlight_probe_max()
3674 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); in drm_edp_backlight_probe_max()
3676 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", in drm_edp_backlight_probe_max()
3677 aux->name, ret); in drm_edp_backlight_probe_max()
3687 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_probe_max()
3689 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3693 for (pn = pn_max; pn >= pn_min; pn--) { in drm_edp_backlight_probe_max()
3700 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); in drm_edp_backlight_probe_max()
3702 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_probe_max()
3703 aux->name, ret); in drm_edp_backlight_probe_max()
3706 bl->pwmgen_bit_count = pn; in drm_edp_backlight_probe_max()
3707 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3710 bl->pwm_freq_pre_divider = f; in drm_edp_backlight_probe_max()
3711 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", in drm_edp_backlight_probe_max()
3712 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3719 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, in drm_edp_backlight_probe_state() argument
3726 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); in drm_edp_backlight_probe_state()
3728 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", in drm_edp_backlight_probe_state()
3729 aux->name, ret); in drm_edp_backlight_probe_state()
3730 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3734 if (!bl->aux_set) in drm_edp_backlight_probe_state()
3738 int size = 1 + bl->lsb_reg_used; in drm_edp_backlight_probe_state()
3740 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); in drm_edp_backlight_probe_state()
3742 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", in drm_edp_backlight_probe_state()
3743 aux->name, ret); in drm_edp_backlight_probe_state()
3744 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3747 if (bl->lsb_reg_used) in drm_edp_backlight_probe_state()
3757 return bl->max; in drm_edp_backlight_probe_state()
3761 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3763 * @aux: The DP aux device to use for probing
3770 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3773 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3779 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, in drm_edp_backlight_init() argument
3786 bl->aux_enable = true; in drm_edp_backlight_init()
3788 bl->aux_set = true; in drm_edp_backlight_init()
3790 bl->lsb_reg_used = true; in drm_edp_backlight_init()
3793 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { in drm_edp_backlight_init()
3794 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3795 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", in drm_edp_backlight_init()
3796 aux->name); in drm_edp_backlight_init()
3797 return -EINVAL; in drm_edp_backlight_init()
3800 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); in drm_edp_backlight_init()
3804 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); in drm_edp_backlight_init()
3809 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3811 aux->name, bl->aux_set, bl->aux_enable, *current_mode); in drm_edp_backlight_init()
3812 if (bl->aux_set) { in drm_edp_backlight_init()
3813 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
3815 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, in drm_edp_backlight_init()
3816 bl->lsb_reg_used); in drm_edp_backlight_init()
3833 if (!bl->enabled) { in dp_aux_backlight_update_status()
3834 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
3835 bl->enabled = true; in dp_aux_backlight_update_status()
3838 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
3840 if (bl->enabled) { in dp_aux_backlight_update_status()
3841 drm_edp_backlight_disable(bl->aux, &bl->info); in dp_aux_backlight_update_status()
3842 bl->enabled = false; in dp_aux_backlight_update_status()
3854 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3856 * @aux: The DP AUX channel to use
3859 * supports backlight control over DP AUX channel using DPCD
3869 * control over DP AUX will call this function at probe time.
3877 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) in drm_panel_dp_aux_backlight() argument
3886 if (!panel || !panel->dev || !aux) in drm_panel_dp_aux_backlight()
3887 return -EINVAL; in drm_panel_dp_aux_backlight()
3889 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, in drm_panel_dp_aux_backlight()
3895 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); in drm_panel_dp_aux_backlight()
3899 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); in drm_panel_dp_aux_backlight()
3901 return -ENOMEM; in drm_panel_dp_aux_backlight()
3903 bl->aux = aux; in drm_panel_dp_aux_backlight()
3905 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, in drm_panel_dp_aux_backlight()
3912 props.max_brightness = bl->info.max; in drm_panel_dp_aux_backlight()
3914 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", in drm_panel_dp_aux_backlight()
3915 panel->dev, bl, in drm_panel_dp_aux_backlight()
3917 if (IS_ERR(bl->base)) in drm_panel_dp_aux_backlight()
3918 return PTR_ERR(bl->base); in drm_panel_dp_aux_backlight()
3920 backlight_disable(bl->base); in drm_panel_dp_aux_backlight()
3922 panel->backlight = bl->base; in drm_panel_dp_aux_backlight()
3930 /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
3952 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
3953 * @lane_count: DP link lane count
3959 * Calculate the BW allocation overhead of a DP link stream, depending
3961 * - @lane_count
3962 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
3963 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
3964 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
3965 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
3967 * - @hactive timing
3968 * - @bpp_x16 color depth
3969 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
3986 * DP Standard v2.1 2.6.4.1 in drm_dp_bw_overhead()
3994 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4: in drm_dp_bw_overhead()
3996 * After each 250 data symbols on 2-4 lanes: in drm_dp_bw_overhead()
4000 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: in drm_dp_bw_overhead()
4010 * DP Standard v2.1 2.7.9, 5.9.7 in drm_dp_bw_overhead()
4034 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4037 * Return the channel coding efficiency of the given DP link type, which is
4039 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4041 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4045 * Returns the efficiency in the 100%/coding-overhead% ratio in