36 #define BLOCK_INFO_N_SUBBLKS(x)	((x) & 0x000F)  argument
37 #define BLOCK_INFO_BLK_ID(x)	(((x) & 0x00F0) >> 4)  argument
38 #define BLOCK_INFO_BLK_TYPE(x)	(((x) & 0xFF00) >> 8)  argument
39 #define BLOCK_INFO_INPUT_ID(x)	((x) & 0xFFF0)  argument
40 #define BLOCK_INFO_TYPE_ID(x)	(((x) & 0x0FF0) >> 4)  argument
42 #define PIPELINE_INFO_N_OUTPUTS(x)	((x) & 0x000F)  argument
43 #define PIPELINE_INFO_N_VALID_INPUTS(x)	(((x) & 0x0F00) >> 8)  argument
60 #define AD_TH			BIT(4)
72 #define GCU_CONTROL_MODE(x)	((x) & 0x7)  argument
80 #define GCU_MAX_LINE_SIZE(x)	((x) & 0xFFFF)  argument
81 #define GCU_MAX_NUM_LINES(x)	((x) >> 16)  argument
82 #define GCU_NUM_RICH_LAYERS(x)	((x) & 0x7)  argument
83 #define GCU_NUM_PIPELINES(x)	(((x) >> 3) & 0x7)  argument
84 #define GCU_NUM_SCALERS(x)	(((x) >> 6) & 0x7)  argument
85 #define GCU_DISPLAY_SPLIT_EN(x)	(((x) >> 16) & 0x1)  argument
86 #define GCU_DISPLAY_TBU_EN(x)	(((x) >> 17) & 0x1)  argument
93 #define DO1_ACTIVE_MODE		4
129 #define GCU_IRQ_MODE		BIT(4)
133 #define GCU_STATUS_MODE(x)	((x) & 0x7)  argument
134 #define GCU_STATUS_MERR		BIT(4)
144 #define PERIPH_NUM_RICH_LAYERS	BIT(4)
157 #define TO_RAXI_AOUTSTDCAPB(x)	(x)  argument
158 #define TO_RAXI_BOUTSTDCAPB(x)	((x) << 8)  argument
159 #define TO_RAXI_BEN(x)		((x) << 15)  argument
160 #define TO_xAXI_BURSTLEN(x)	((x) << 16)  argument
161 #define TO_xAXI_AxQOS(x)	((x) << 24)  argument
162 #define TO_xAXI_ORD(x)		((x) << 31)  argument
163 #define TO_WAXI_OUTSTDCAPB(x)	(x)  argument
174 #define TO_TBU_DOUTSTDCAPB(x)	(x)  argument
185 #define LPU_STATUS_AXIED(x)	((x) & 0xF)  argument
186 #define LPU_STATUS_AXIE		BIT(4)
203 #define TO_AXIE(x)		((x) << 4)  argument
240 #define CU_PER_INPUT_REGS	4
262 #define CU_INPUT_CTRL_ALPHA(x)	(((x) & 0xFF) << 8)  argument
295 #define L_IT			BIT(4)
298 #define L_ROT(x)		(((x) & 3) << 8)  argument
302 #define L_A_RCACHE(x)		(((x) & 0xF) << 28)  argument
314 #define L_ITSEL(x)		((x) & 0xFFF)  argument
315 #define L_FTSEL(x)		(((x) & 0xFFF) << 16)  argument
317 #define LAYER_PER_PLANE_REGS	4
324 #define LW_OFM			BIT(4)
325 #define LW_LALPHA(x)		(((x) & 0xFF) << 8)  argument
326 #define LW_A_WCACHE(x)		(((x) & 0xF) << 28)  argument
340 #define L_INFO_ABUF_SIZE(x)	(((x) >> 4) & 0x7)  argument
341 #define L_INFO_YUV_MAX_LINESZ(x)	(((x) >> 16) & 0xFFFF)  argument
360 #define SC_CTRL_AP		BIT(4)
375 #define MG_INPUT_ID1		(MG_INPUT_ID0 + 4)
406 #define BS_CTRL_HMASK		BIT(4)
421 #define BS_SYNC_HSW(x)		((x) & 0x3FF)  argument
423 #define BS_SYNC_VSW(x)		(((x) & 0xFF) << 16)  argument
438 #define IPS_CTRL_FT		BIT(4)
469 #define SC_COEFF_DATA(x, y)	(((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))  argument
499 #define D71_PIPELINE_MAX_LAYERS		4
502 #define D71_MAX_GLB_SCL_COEFF		4
504 #define D71_MAX_LAYERS_PER_LPU		4
520 #define D71_MG_MIN_MERGED_SIZE		4