Lines Matching +full:fan +full:- +full:controller
33 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
36 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
39 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
42 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
45 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
48 …((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
127 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
129 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
131 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
140 if (adev->powerplay.pp_funcs->print_power_state == NULL) in amdgpu_pm_print_power_states()
143 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
144 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
161 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_get_platform_caps()
167 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_get_platform_caps()
169 return -EINVAL; in amdgpu_get_platform_caps()
170 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in amdgpu_get_platform_caps()
172 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
173 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
174 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
180 struct _ATOM_PPLIB_FANTABLE fan; member
188 u32 size = atom_table->ucNumEntries * in amdgpu_parse_clk_voltage_dep_table()
193 amdgpu_table->entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_clk_voltage_dep_table()
194 if (!amdgpu_table->entries) in amdgpu_parse_clk_voltage_dep_table()
195 return -ENOMEM; in amdgpu_parse_clk_voltage_dep_table()
197 entry = &atom_table->entries[0]; in amdgpu_parse_clk_voltage_dep_table()
198 for (i = 0; i < atom_table->ucNumEntries; i++) { in amdgpu_parse_clk_voltage_dep_table()
199 amdgpu_table->entries[i].clk = le16_to_cpu(entry->usClockLow) | in amdgpu_parse_clk_voltage_dep_table()
200 (entry->ucClockHigh << 16); in amdgpu_parse_clk_voltage_dep_table()
201 amdgpu_table->entries[i].v = le16_to_cpu(entry->usVoltage); in amdgpu_parse_clk_voltage_dep_table()
205 amdgpu_table->count = atom_table->ucNumEntries; in amdgpu_parse_clk_voltage_dep_table()
222 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_parse_extended_power_table()
231 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_parse_extended_power_table()
233 return -EINVAL; in amdgpu_parse_extended_power_table()
234 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in amdgpu_parse_extended_power_table()
236 /* fan table */ in amdgpu_parse_extended_power_table()
237 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
239 if (power_info->pplib3.usFanTableOffset) { in amdgpu_parse_extended_power_table()
240 fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
241 le16_to_cpu(power_info->pplib3.usFanTableOffset)); in amdgpu_parse_extended_power_table()
242 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
243 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
244 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
245 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
246 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in amdgpu_parse_extended_power_table()
247 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in amdgpu_parse_extended_power_table()
248 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in amdgpu_parse_extended_power_table()
249 if (fan_info->fan.ucFanTableFormat >= 2) in amdgpu_parse_extended_power_table()
250 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in amdgpu_parse_extended_power_table()
252 adev->pm.dpm.fan.t_max = 10900; in amdgpu_parse_extended_power_table()
253 adev->pm.dpm.fan.cycle_delay = 100000; in amdgpu_parse_extended_power_table()
254 if (fan_info->fan.ucFanTableFormat >= 3) { in amdgpu_parse_extended_power_table()
255 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in amdgpu_parse_extended_power_table()
256 adev->pm.dpm.fan.default_max_fan_pwm = in amdgpu_parse_extended_power_table()
257 le16_to_cpu(fan_info->fan3.usFanPWMMax); in amdgpu_parse_extended_power_table()
258 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in amdgpu_parse_extended_power_table()
259 adev->pm.dpm.fan.fan_output_sensitivity = in amdgpu_parse_extended_power_table()
260 le16_to_cpu(fan_info->fan3.usFanOutputSensitivity); in amdgpu_parse_extended_power_table()
262 adev->pm.dpm.fan.ucode_fan_control = true; in amdgpu_parse_extended_power_table()
267 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
269 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { in amdgpu_parse_extended_power_table()
271 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
272 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); in amdgpu_parse_extended_power_table()
273 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
278 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
280 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
281 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
282 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
287 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
289 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
290 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
291 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
296 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
298 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
299 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
300 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
305 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { in amdgpu_parse_extended_power_table()
308 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
309 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset)); in amdgpu_parse_extended_power_table()
310 if (clk_v->ucNumEntries) { in amdgpu_parse_extended_power_table()
311 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
312 le16_to_cpu(clk_v->entries[0].usSclkLow) | in amdgpu_parse_extended_power_table()
313 (clk_v->entries[0].ucSclkHigh << 16); in amdgpu_parse_extended_power_table()
314 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
315 le16_to_cpu(clk_v->entries[0].usMclkLow) | in amdgpu_parse_extended_power_table()
316 (clk_v->entries[0].ucMclkHigh << 16); in amdgpu_parse_extended_power_table()
317 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
318 le16_to_cpu(clk_v->entries[0].usVddc); in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
320 le16_to_cpu(clk_v->entries[0].usVddci); in amdgpu_parse_extended_power_table()
323 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) { in amdgpu_parse_extended_power_table()
326 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
327 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset)); in amdgpu_parse_extended_power_table()
330 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
331 kcalloc(psl->ucNumEntries, in amdgpu_parse_extended_power_table()
334 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) in amdgpu_parse_extended_power_table()
335 return -ENOMEM; in amdgpu_parse_extended_power_table()
337 entry = &psl->entries[0]; in amdgpu_parse_extended_power_table()
338 for (i = 0; i < psl->ucNumEntries; i++) { in amdgpu_parse_extended_power_table()
339 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
340 le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16); in amdgpu_parse_extended_power_table()
341 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in amdgpu_parse_extended_power_table()
342 le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16); in amdgpu_parse_extended_power_table()
343 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in amdgpu_parse_extended_power_table()
344 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
348 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in amdgpu_parse_extended_power_table()
349 psl->ucNumEntries; in amdgpu_parse_extended_power_table()
354 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
356 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in amdgpu_parse_extended_power_table()
357 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in amdgpu_parse_extended_power_table()
358 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; in amdgpu_parse_extended_power_table()
359 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in amdgpu_parse_extended_power_table()
360 if (adev->pm.dpm.tdp_od_limit) in amdgpu_parse_extended_power_table()
361 adev->pm.dpm.power_control = true; in amdgpu_parse_extended_power_table()
363 adev->pm.dpm.power_control = false; in amdgpu_parse_extended_power_table()
364 adev->pm.dpm.tdp_adjustment = 0; in amdgpu_parse_extended_power_table()
365 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in amdgpu_parse_extended_power_table()
366 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in amdgpu_parse_extended_power_table()
367 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in amdgpu_parse_extended_power_table()
368 if (power_info->pplib5.usCACLeakageTableOffset) { in amdgpu_parse_extended_power_table()
371 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
372 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset)); in amdgpu_parse_extended_power_table()
374 u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table); in amdgpu_parse_extended_power_table()
375 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_extended_power_table()
376 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) in amdgpu_parse_extended_power_table()
377 return -ENOMEM; in amdgpu_parse_extended_power_table()
378 entry = &cac_table->entries[0]; in amdgpu_parse_extended_power_table()
379 for (i = 0; i < cac_table->ucNumEntries; i++) { in amdgpu_parse_extended_power_table()
380 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in amdgpu_parse_extended_power_table()
381 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in amdgpu_parse_extended_power_table()
382 le16_to_cpu(entry->usVddc1); in amdgpu_parse_extended_power_table()
383 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in amdgpu_parse_extended_power_table()
384 le16_to_cpu(entry->usVddc2); in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in amdgpu_parse_extended_power_table()
386 le16_to_cpu(entry->usVddc3); in amdgpu_parse_extended_power_table()
388 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in amdgpu_parse_extended_power_table()
389 le16_to_cpu(entry->usVddc); in amdgpu_parse_extended_power_table()
390 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in amdgpu_parse_extended_power_table()
391 le32_to_cpu(entry->ulLeakageValue); in amdgpu_parse_extended_power_table()
396 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in amdgpu_parse_extended_power_table()
401 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
404 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
405 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset)); in amdgpu_parse_extended_power_table()
406 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) && in amdgpu_parse_extended_power_table()
407 ext_hdr->usVCETableOffset) { in amdgpu_parse_extended_power_table()
409 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
410 le16_to_cpu(ext_hdr->usVCETableOffset) + 1); in amdgpu_parse_extended_power_table()
413 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
414 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in amdgpu_parse_extended_power_table()
415 1 + array->ucNumEntries * sizeof(VCEClockInfo)); in amdgpu_parse_extended_power_table()
418 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
419 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in amdgpu_parse_extended_power_table()
420 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) + in amdgpu_parse_extended_power_table()
421 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); in amdgpu_parse_extended_power_table()
425 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
427 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
429 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) in amdgpu_parse_extended_power_table()
430 return -ENOMEM; in amdgpu_parse_extended_power_table()
431 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
432 limits->numEntries; in amdgpu_parse_extended_power_table()
433 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
434 state_entry = &states->entries[0]; in amdgpu_parse_extended_power_table()
435 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
437 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
438 (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in amdgpu_parse_extended_power_table()
439 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
440 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in amdgpu_parse_extended_power_table()
441 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
442 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in amdgpu_parse_extended_power_table()
443 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
444 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
448 adev->pm.dpm.num_of_vce_states = in amdgpu_parse_extended_power_table()
449 states->numEntries > AMD_MAX_VCE_LEVELS ? in amdgpu_parse_extended_power_table()
450 AMD_MAX_VCE_LEVELS : states->numEntries; in amdgpu_parse_extended_power_table()
451 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in amdgpu_parse_extended_power_table()
453 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
454 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in amdgpu_parse_extended_power_table()
455 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
456 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in amdgpu_parse_extended_power_table()
457 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
458 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in amdgpu_parse_extended_power_table()
459 adev->pm.dpm.vce_states[i].clk_idx = in amdgpu_parse_extended_power_table()
460 state_entry->ucClockInfoIndex & 0x3f; in amdgpu_parse_extended_power_table()
461 adev->pm.dpm.vce_states[i].pstate = in amdgpu_parse_extended_power_table()
462 (state_entry->ucClockInfoIndex & 0xc0) >> 6; in amdgpu_parse_extended_power_table()
467 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && in amdgpu_parse_extended_power_table()
468 ext_hdr->usUVDTableOffset) { in amdgpu_parse_extended_power_table()
470 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
471 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); in amdgpu_parse_extended_power_table()
474 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
475 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + in amdgpu_parse_extended_power_table()
476 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); in amdgpu_parse_extended_power_table()
478 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
480 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
482 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) in amdgpu_parse_extended_power_table()
483 return -ENOMEM; in amdgpu_parse_extended_power_table()
484 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
485 limits->numEntries; in amdgpu_parse_extended_power_table()
486 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
487 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
489 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
490 (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo))); in amdgpu_parse_extended_power_table()
491 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in amdgpu_parse_extended_power_table()
492 le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); in amdgpu_parse_extended_power_table()
493 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in amdgpu_parse_extended_power_table()
494 le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); in amdgpu_parse_extended_power_table()
495 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
496 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
501 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) && in amdgpu_parse_extended_power_table()
502 ext_hdr->usSAMUTableOffset) { in amdgpu_parse_extended_power_table()
505 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
506 le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1); in amdgpu_parse_extended_power_table()
508 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
510 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
512 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) in amdgpu_parse_extended_power_table()
513 return -ENOMEM; in amdgpu_parse_extended_power_table()
514 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
515 limits->numEntries; in amdgpu_parse_extended_power_table()
516 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
517 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
518 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
519 le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16); in amdgpu_parse_extended_power_table()
520 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
521 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
526 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && in amdgpu_parse_extended_power_table()
527 ext_hdr->usPPMTableOffset) { in amdgpu_parse_extended_power_table()
529 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
530 le16_to_cpu(ext_hdr->usPPMTableOffset)); in amdgpu_parse_extended_power_table()
531 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
533 if (!adev->pm.dpm.dyn_state.ppm_table) in amdgpu_parse_extended_power_table()
534 return -ENOMEM; in amdgpu_parse_extended_power_table()
535 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in amdgpu_parse_extended_power_table()
536 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in amdgpu_parse_extended_power_table()
537 le16_to_cpu(ppm->usCpuCoreNumber); in amdgpu_parse_extended_power_table()
538 adev->pm.dpm.dyn_state.ppm_table->platform_tdp = in amdgpu_parse_extended_power_table()
539 le32_to_cpu(ppm->ulPlatformTDP); in amdgpu_parse_extended_power_table()
540 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in amdgpu_parse_extended_power_table()
541 le32_to_cpu(ppm->ulSmallACPlatformTDP); in amdgpu_parse_extended_power_table()
542 adev->pm.dpm.dyn_state.ppm_table->platform_tdc = in amdgpu_parse_extended_power_table()
543 le32_to_cpu(ppm->ulPlatformTDC); in amdgpu_parse_extended_power_table()
544 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in amdgpu_parse_extended_power_table()
545 le32_to_cpu(ppm->ulSmallACPlatformTDC); in amdgpu_parse_extended_power_table()
546 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
547 le32_to_cpu(ppm->ulApuTDP); in amdgpu_parse_extended_power_table()
548 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
549 le32_to_cpu(ppm->ulDGpuTDP); in amdgpu_parse_extended_power_table()
550 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in amdgpu_parse_extended_power_table()
551 le32_to_cpu(ppm->ulDGpuUlvPower); in amdgpu_parse_extended_power_table()
552 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
553 le32_to_cpu(ppm->ulTjmax); in amdgpu_parse_extended_power_table()
555 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) && in amdgpu_parse_extended_power_table()
556 ext_hdr->usACPTableOffset) { in amdgpu_parse_extended_power_table()
559 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
560 le16_to_cpu(ext_hdr->usACPTableOffset) + 1); in amdgpu_parse_extended_power_table()
562 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
564 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
566 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) in amdgpu_parse_extended_power_table()
567 return -ENOMEM; in amdgpu_parse_extended_power_table()
568 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
569 limits->numEntries; in amdgpu_parse_extended_power_table()
570 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
571 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
572 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
573 le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16); in amdgpu_parse_extended_power_table()
574 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
575 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
580 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) && in amdgpu_parse_extended_power_table()
581 ext_hdr->usPowerTuneTableOffset) { in amdgpu_parse_extended_power_table()
582 u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
583 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
585 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
587 if (!adev->pm.dpm.dyn_state.cac_tdp_table) in amdgpu_parse_extended_power_table()
588 return -ENOMEM; in amdgpu_parse_extended_power_table()
591 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
592 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
593 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in amdgpu_parse_extended_power_table()
594 ppt->usMaximumPowerDeliveryLimit; in amdgpu_parse_extended_power_table()
595 pt = &ppt->power_tune_table; in amdgpu_parse_extended_power_table()
598 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
599 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
600 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in amdgpu_parse_extended_power_table()
601 pt = &ppt->power_tune_table; in amdgpu_parse_extended_power_table()
603 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in amdgpu_parse_extended_power_table()
604 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in amdgpu_parse_extended_power_table()
605 le16_to_cpu(pt->usConfigurableTDP); in amdgpu_parse_extended_power_table()
606 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in amdgpu_parse_extended_power_table()
607 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in amdgpu_parse_extended_power_table()
608 le16_to_cpu(pt->usBatteryPowerLimit); in amdgpu_parse_extended_power_table()
609 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in amdgpu_parse_extended_power_table()
610 le16_to_cpu(pt->usSmallPowerLimit); in amdgpu_parse_extended_power_table()
611 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in amdgpu_parse_extended_power_table()
612 le16_to_cpu(pt->usLowCACLeakage); in amdgpu_parse_extended_power_table()
613 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in amdgpu_parse_extended_power_table()
614 le16_to_cpu(pt->usHighCACLeakage); in amdgpu_parse_extended_power_table()
616 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8) && in amdgpu_parse_extended_power_table()
617 ext_hdr->usSclkVddgfxTableOffset) { in amdgpu_parse_extended_power_table()
619 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
620 le16_to_cpu(ext_hdr->usSclkVddgfxTableOffset)); in amdgpu_parse_extended_power_table()
622 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, in amdgpu_parse_extended_power_table()
634 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table()
636 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
637 kfree(dyn_state->vddci_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
638 kfree(dyn_state->vddc_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
639 kfree(dyn_state->mvdd_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
640 kfree(dyn_state->cac_leakage_table.entries); in amdgpu_free_extended_power_table()
641 kfree(dyn_state->phase_shedding_limits_table.entries); in amdgpu_free_extended_power_table()
642 kfree(dyn_state->ppm_table); in amdgpu_free_extended_power_table()
643 kfree(dyn_state->cac_tdp_table); in amdgpu_free_extended_power_table()
644 kfree(dyn_state->vce_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
645 kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
646 kfree(dyn_state->samu_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
647 kfree(dyn_state->acp_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
648 kfree(dyn_state->vddgfx_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
676 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_add_thermal_controller()
679 ATOM_PPLIB_THERMALCONTROLLER *controller; in amdgpu_add_thermal_controller() local
684 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_add_thermal_controller()
688 (mode_info->atom_context->bios + data_offset); in amdgpu_add_thermal_controller()
689 controller = &power_table->sThermalController; in amdgpu_add_thermal_controller()
691 /* add the i2c bus for thermal/fan chip */ in amdgpu_add_thermal_controller()
692 if (controller->ucType > 0) { in amdgpu_add_thermal_controller()
693 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) in amdgpu_add_thermal_controller()
694 adev->pm.no_fan = true; in amdgpu_add_thermal_controller()
695 adev->pm.fan_pulses_per_revolution = in amdgpu_add_thermal_controller()
696 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; in amdgpu_add_thermal_controller()
697 if (adev->pm.fan_pulses_per_revolution) { in amdgpu_add_thermal_controller()
698 adev->pm.fan_min_rpm = controller->ucFanMinRPM; in amdgpu_add_thermal_controller()
699 adev->pm.fan_max_rpm = controller->ucFanMaxRPM; in amdgpu_add_thermal_controller()
701 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { in amdgpu_add_thermal_controller()
702 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
703 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
705 adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; in amdgpu_add_thermal_controller()
706 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { in amdgpu_add_thermal_controller()
707 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
708 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
710 adev->pm.int_thermal_type = THERMAL_TYPE_RV770; in amdgpu_add_thermal_controller()
711 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { in amdgpu_add_thermal_controller()
712 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
713 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
715 adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; in amdgpu_add_thermal_controller()
716 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { in amdgpu_add_thermal_controller()
717 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
718 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
720 adev->pm.int_thermal_type = THERMAL_TYPE_SUMO; in amdgpu_add_thermal_controller()
721 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { in amdgpu_add_thermal_controller()
722 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
723 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
725 adev->pm.int_thermal_type = THERMAL_TYPE_NI; in amdgpu_add_thermal_controller()
726 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { in amdgpu_add_thermal_controller()
727 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
728 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
730 adev->pm.int_thermal_type = THERMAL_TYPE_SI; in amdgpu_add_thermal_controller()
731 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { in amdgpu_add_thermal_controller()
732 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
733 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
735 adev->pm.int_thermal_type = THERMAL_TYPE_CI; in amdgpu_add_thermal_controller()
736 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { in amdgpu_add_thermal_controller()
737 DRM_INFO("Internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
738 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
740 adev->pm.int_thermal_type = THERMAL_TYPE_KV; in amdgpu_add_thermal_controller()
741 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { in amdgpu_add_thermal_controller()
742 DRM_INFO("External GPIO thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
743 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
745 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; in amdgpu_add_thermal_controller()
746 } else if (controller->ucType == in amdgpu_add_thermal_controller()
748 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
749 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
751 adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; in amdgpu_add_thermal_controller()
752 } else if (controller->ucType == in amdgpu_add_thermal_controller()
754 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
755 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
757 adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; in amdgpu_add_thermal_controller()
758 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { in amdgpu_add_thermal_controller()
759 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", in amdgpu_add_thermal_controller()
760 pp_lib_thermal_controller_names[controller->ucType], in amdgpu_add_thermal_controller()
761 controller->ucI2cAddress >> 1, in amdgpu_add_thermal_controller()
762 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
764 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; in amdgpu_add_thermal_controller()
765 i2c_bus = amdgpu_atombios_lookup_i2c_gpio(adev, controller->ucI2cLine); in amdgpu_add_thermal_controller()
766 adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus); in amdgpu_add_thermal_controller()
767 if (adev->pm.i2c_bus) { in amdgpu_add_thermal_controller()
769 const char *name = pp_lib_thermal_controller_names[controller->ucType]; in amdgpu_add_thermal_controller()
770 info.addr = controller->ucI2cAddress >> 1; in amdgpu_add_thermal_controller()
772 i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info); in amdgpu_add_thermal_controller()
775 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", in amdgpu_add_thermal_controller()
776 controller->ucType, in amdgpu_add_thermal_controller()
777 controller->ucI2cAddress >> 1, in amdgpu_add_thermal_controller()
778 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
788 if (idx < adev->pm.dpm.num_of_vce_states) in amdgpu_get_vce_clock_state()
789 return &adev->pm.dpm.vce_states[idx]; in amdgpu_get_vce_clock_state()
800 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? in amdgpu_dpm_pick_power_state()
804 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { in amdgpu_dpm_pick_power_state()
820 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in amdgpu_dpm_pick_power_state()
821 ps = &adev->pm.dpm.ps[i]; in amdgpu_dpm_pick_power_state()
822 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; in amdgpu_dpm_pick_power_state()
827 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
836 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
845 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
854 if (adev->pm.dpm.uvd_ps) in amdgpu_dpm_pick_power_state()
855 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
859 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) in amdgpu_dpm_pick_power_state()
863 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) in amdgpu_dpm_pick_power_state()
867 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) in amdgpu_dpm_pick_power_state()
871 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in amdgpu_dpm_pick_power_state()
875 return adev->pm.dpm.boot_ps; in amdgpu_dpm_pick_power_state()
877 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) in amdgpu_dpm_pick_power_state()
881 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) in amdgpu_dpm_pick_power_state()
885 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in amdgpu_dpm_pick_power_state()
889 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) in amdgpu_dpm_pick_power_state()
904 if (adev->pm.dpm.uvd_ps) { in amdgpu_dpm_pick_power_state()
905 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
930 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_change_power_state_locked()
937 if (!adev->pm.dpm_enabled) in amdgpu_dpm_change_power_state_locked()
940 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
942 if ((!adev->pm.dpm.thermal_active) && in amdgpu_dpm_change_power_state_locked()
943 (!adev->pm.dpm.uvd_active)) in amdgpu_dpm_change_power_state_locked()
944 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
946 dpm_state = adev->pm.dpm.state; in amdgpu_dpm_change_power_state_locked()
950 adev->pm.dpm.requested_ps = ps; in amdgpu_dpm_change_power_state_locked()
952 return -EINVAL; in amdgpu_dpm_change_power_state_locked()
954 if (amdgpu_dpm == 1 && pp_funcs->print_power_state) { in amdgpu_dpm_change_power_state_locked()
956 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
958 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
962 ps->vce_active = adev->pm.dpm.vce_active; in amdgpu_dpm_change_power_state_locked()
963 if (pp_funcs->display_configuration_changed) in amdgpu_dpm_change_power_state_locked()
970 if (pp_funcs->check_state_equal) { in amdgpu_dpm_change_power_state_locked()
971 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
978 if (pp_funcs->set_power_state) in amdgpu_dpm_change_power_state_locked()
979 pp_funcs->set_power_state(adev->powerplay.pp_handle); in amdgpu_dpm_change_power_state_locked()
983 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
984 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; in amdgpu_dpm_change_power_state_locked()
986 if (pp_funcs->force_performance_level) { in amdgpu_dpm_change_power_state_locked()
987 if (adev->pm.dpm.thermal_active) { in amdgpu_dpm_change_power_state_locked()
988 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_dpm_change_power_state_locked()
990 pp_funcs->force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); in amdgpu_dpm_change_power_state_locked()
992 adev->pm.dpm.forced_level = level; in amdgpu_dpm_change_power_state_locked()
995 pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level); in amdgpu_dpm_change_power_state_locked()
1016 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_thermal_work_handler()
1021 if (!adev->pm.dpm_enabled) in amdgpu_dpm_thermal_work_handler()
1024 if (!pp_funcs->read_sensor(adev->powerplay.pp_handle, in amdgpu_dpm_thermal_work_handler()
1028 if (temp < adev->pm.dpm.thermal.min_temp) in amdgpu_dpm_thermal_work_handler()
1030 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1032 if (adev->pm.dpm.thermal.high_to_low) in amdgpu_dpm_thermal_work_handler()
1034 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1038 adev->pm.dpm.thermal_active = true; in amdgpu_dpm_thermal_work_handler()
1040 adev->pm.dpm.thermal_active = false; in amdgpu_dpm_thermal_work_handler()
1042 adev->pm.dpm.state = dpm_state; in amdgpu_dpm_thermal_work_handler()
1044 amdgpu_legacy_dpm_compute_clocks(adev->powerplay.pp_handle); in amdgpu_dpm_thermal_work_handler()