52 #define MCP_ABM_LEVEL_SET 0x65
53 #define MCP_ABM_PIPE_SET 0x66
54 #define MCP_BL_SET 0x67
61 	uint32_t rampingBoundary = 0xFFFF;  in dce_abm_set_pipe()
66 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,  in dce_abm_set_pipe()
80 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,  in dce_abm_set_pipe()
93 	unsigned int backlight_8_bit = 0;  in dmcu_set_backlight_level()
96 	if (backlight_pwm_u16_16 & 0x10000)  in dmcu_set_backlight_level()
98 		backlight_8_bit = 0xFF;  in dmcu_set_backlight_level()
101 		backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;  in dmcu_set_backlight_level()
107 			0, 1, 80000);  in dmcu_set_backlight_level()
113 	if (controller_id == 0)  in dmcu_set_backlight_level()
114 		frame_ramp = 0;  in dmcu_set_backlight_level()
135 			0, 1, 80000);  in dmcu_set_backlight_level()
142 	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);  in dce_abm_init()
143 	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);  in dce_abm_init()
144 	REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);  in dce_abm_init()
145 	REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);  in dce_abm_init()
146 	REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);  in dce_abm_init()
148 	REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,  in dce_abm_init()
149 			ABM1_HG_NUM_OF_BINS_SEL, 0,  in dce_abm_init()
151 			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);  in dce_abm_init()
153 	REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,  in dce_abm_init()
168 			ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,  in dce_abm_init()
171 	REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,  in dce_abm_init()
206 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,  in dce_abm_set_level()
239 	DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",  in dce_abm_set_backlight_level_pwm()