display/dc/dc.h

2  * Copyright 2012-2023 Advanced Micro Devices, Inc.
103 	// for example, 1080p -> 8K is 4.0, or 4000 raw value
111 	// for example, 8K -> 1080p is 0.25, or 250 raw value
123  * DOC: color-management-caps
128  * abstracted HW. DCE 5-12 had almost no important changes, but starting with
135  * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
151  * struct dpp_color_caps - color pipeline capabilities for display pipe and
156  * just plain 256-entry lookup
165  * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
166  * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
167  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
187  * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
196  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
208  * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
356  * re-programming however do not affect bandwidth consumption or clock
480  * enum pipe_split_policy - Pipe split strategy supported by DCN
488 	 * pipe in order to bring the best trade-off between performance and
520 	DCN_PWR_STATE_UNKNOWN = -1,
535  * struct dc_clocks - DC pipe clocks
603 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
604 				dm_get_timestamp(dc->ctx) : 0
607 		if (dc->debug.bw_val_profile.enable) \
608 			dc->debug.bw_val_profile.total_count++
611 		if (dc->debug.bw_val_profile.enable) { \
613 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
614 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
618 		if (dc->debug.bw_val_profile.enable) \
619 			voltage_level_tick = dm_get_timestamp(dc->ctx)
622 		if (dc->debug.bw_val_profile.enable) \
623 			watermark_tick = dm_get_timestamp(dc->ctx)
626 		if (dc->debug.bw_val_profile.enable) { \
627 			end_tick = dm_get_timestamp(dc->ctx); \
628 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
629 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
631 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
632 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
639 		bool i2c: 1;  member
730  * 15-2: reserved
731  * 31-16: timeout in ms
804  * struct dc_debug_options - DC debug struct
914 	/* TODO - remove once tested */
1421  * struct dc_validation_set - Struct to store surface/stream associations for validation
1491  * return - minimum required timing bandwidth in kbps.
1500  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1678  * @reason - Indicate which event triggers this detection. dc may customize
1680  * return false - if detection is not fully completed. This could happen when
1683  * link->connection_type == dc_connection_mst_branch when returning false).
1684  * return true - detection is completed, link has been fully updated with latest
1696  * @dc_link - link the remote sink will be added to.
1697  * @edid - byte array of EDID raw data.
1698  * @len - size of the edid in byte
1699  * @init_data -
1708  * @link - link the sink should be removed from
1709  * @sink - sink to be removed.
1723  * @type - dc_connection_single if connected, dc_connection_none otherwise.
1724  * return - false if an unexpected error occurs, true otherwise.
1735  * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1745  * @link - The link the HPD pin is associated with.
1746  * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1753  * @enable = false - disable hardware HPD filter. HPD event will be queued
1759 /* submit i2c read/write payloads through ddc channel
1760  * @link_index - index to a link with ddc in i2c mode
1761  * @cmd - i2c command structure
1762  * return - true if success, false otherwise.
1769 /* submit i2c read/write payloads through oem channel
1770  * @link_index - index to a link with ddc in i2c mode
1771  * @cmd - i2c command structure
1772  * return - true if success, false otherwise.
1780  * retries or handle error states. The reply is returned in the payload->reply
1782  * transferred,or -1 on a failure.
1799  * TODO - When defer_handling is true the function will have a different purpose.
1804  * true - Downstream port status changed. DM should call DC to do the
1806  * false - no change in Downstream port status. No further action required
1821  * return true - hpd rx irq should be handled.
1822  * return false - it is safe to ignore hpd rx irq event
1827  * @link - link the hpd irq data associated with
1828  * @hpd_irq_dpcd_data - input hpd irq data
1829  * return - true if hpd irq data indicates a link lost
1835  * @link - link where the hpd irq data should be read from
1836  * @irq_data - output hpd irq data
1837  * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1847  * TODO - in the future we should consider to expand link resume interface to
1853 /* Destruct the mst topology of the link and reset the allocated payload table
1856  * still wants to reset MST topology on an unplug event */
1862  * return - total effective link bandwidth in kbps.
1902  * interface i.e stream_update->dsc_config
1910  * @link - current detected link
1911  * @req_bw - requested bandwidth in kbps
1912  * @link_settings - returned most optimal link settings that can fit the
1914  * return - false if link can't support requested bandwidth, true if link
1930  * @link -  a link with DP RX connection
1931  * return - if stream is committed to this link with MST signal type, type of
1940  * @link - a link with DP RX connection
1941  * return - max dp link settings the link can enable.
1949  * @link - a link with DP RX connection
1950  * return - highest encoding format link supports.
1956  * @link - a link with dp connector signal type
1957  * return - true if connected, false otherwise
1961 /* Force DP lane settings update to main-link video signal and notify the change
1966  * @lt_settings - a container structure with desired hw_lane_settings
1973  * test or debugging purpose. The test pattern will remain until next un-plug.
1975  * @link - active link with DP signal output enabled.
1976  * @test_pattern - desired test pattern to output.
1978  * @test_pattern_color_space - for video test pattern choose a desired color
1980  * @p_link_settings - For PHY pattern choose a desired link settings
1981  * @p_custom_pattern - some test pattern will require a custom input to
1983  * @cust_pattern_size - size of the custom pattern input.
2008  * @link_settings - if not NULL, force preferred link settings to the link.
2009  * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2021 /* return - true if FEC is supported with connected DP RX, false otherwise */
2026  * return - true if FEC should be enabled, false otherwise.
2037  * NOTE: this interface doesn't update dp main-link. Calling this function will
2038  * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2041  * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2046 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2047  * current value read from extended receiver cap from 02200h - 0220Fh.
2065 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2111  * return - true if trace is initialized and has valid data. False dp trace
2132  * @in_detection - true to get link training end time stamp of last link
2140  * @in_detection - true to get link training count of last link
2154  * Send a request from DP-Tx requesting to allocate BW remotely after
2181  * Unplug => de-allocate bw
2204 /* Sink Interfaces - A sink corresponds to a display output device */
2209 	// 8 byte port ID -> ELD.PortID
2211 	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2213 	// 2 byte product code -> ELD.ProductCode
2219 	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2223 	// 'true' if MST topology supports DSC passthrough for sink
2224 	// 'false' if MST topology does not support DSC passthrough