display/dc/dc.h

401 struct dc_config {  struct
402 	bool gpu_vm_support;
403 	bool disable_disp_pll_sharing;
404 	bool fbc_support;
405 	bool disable_fractional_pwm;
406 	bool allow_seamless_boot_optimization;
407 	bool seamless_boot_edp_requested;
408 	bool edp_not_connected;
409 	bool edp_no_power_sequencing;
410 	bool force_enum_edp;
411 	bool forced_clocks;
412 	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
413 	bool multi_mon_pp_mclk_switch;
414 	bool disable_dmcu;
415 	bool enable_4to1MPC;
416 	bool enable_windowed_mpo_odm;
417 	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
418 	uint32_t allow_edp_hotplug_detection;
419 	bool clamp_min_dcfclk;
420 	uint64_t vblank_alignment_dto_params;
421 	uint8_t  vblank_alignment_max_frame_time_diff;
422 	bool is_asymmetric_memory;
423 	bool is_single_rank_dimm;
424 	bool is_vmin_only_asic;
425 	bool use_pipe_ctx_sync_logic;
426 	bool ignore_dpref_ss;
427 	bool enable_mipi_converter_optimization;
428 	bool use_default_clock_table;
429 	bool force_bios_enable_lttpr;
430 	uint8_t force_bios_fixed_vs;
431 	int sdpif_request_limit_words_per_umc;
432 	bool use_old_fixed_vs_sequence;
433 	bool dc_mode_clk_limit_support;
434 	bool EnableMinDispClkODM;
435 	bool enable_auto_dpm_test_logs;
436 	unsigned int disable_ips;
437 	unsigned int disable_ips_in_vpb;