Lines Matching full:dm
160 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
216 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
218 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
275 struct dc *dc = adev->dm.dc; in dm_crtc_get_scanoutpos()
375 * dc_update_planes_and_stream function; however, DM might need some
559 adev->dm.freesync_module, in dm_vupdate_high_irq()
564 adev->dm.dc, in dm_vupdate_high_irq()
612 dc_stream_fc_disable_writeback(adev->dm.dc, in dm_crtc_high_irq()
651 mod_freesync_handle_v_update(adev->dm.freesync_module, in dm_crtc_high_irq()
655 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
712 * Copies dmub notification to DM which is to be read by AUX command.
718 if (adev->dm.dmub_notify) in dmub_aux_setconfig_callback()
719 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); in dmub_aux_setconfig_callback()
721 complete(&adev->dm.dmub_aux_transfer_done); in dmub_aux_setconfig_callback()
751 if (notify->link_index > adev->dm.dc->link_count) { in dmub_hpd_callback()
757 link = adev->dm.dc->links[link_index]; in dmub_hpd_callback()
758 dev = adev->dm.ddev; in dmub_hpd_callback()
807 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { in register_dmub_notify_callback()
808 adev->dm.dmub_callback[type] = callback; in register_dmub_notify_callback()
809 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; in register_dmub_notify_callback()
827 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { in dm_handle_hpd_work()
828 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, in dm_handle_hpd_work()
850 struct amdgpu_display_manager *dm = &adev->dm; in dm_dmub_outbox1_low_irq() local
856 if (dc_enable_dmub_notifications(adev->dm.dc) && in dm_dmub_outbox1_low_irq()
860 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); in dm_dmub_outbox1_low_irq()
861 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { in dm_dmub_outbox1_low_irq()
862 DRM_ERROR("DM: notify type %d invalid!", notify.type); in dm_dmub_outbox1_low_irq()
865 if (!dm->dmub_callback[notify.type]) { in dm_dmub_outbox1_low_irq()
869 if (dm->dmub_thread_offload[notify.type] == true) { in dm_dmub_outbox1_low_irq()
885 plink = adev->dm.dc->links[notify.link_index]; in dm_dmub_outbox1_low_irq()
891 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); in dm_dmub_outbox1_low_irq()
893 dm->dmub_callback[notify.type](adev, ¬ify); in dm_dmub_outbox1_low_irq()
900 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { in dm_dmub_outbox1_low_irq()
936 struct dm_compressor_info *compressor = &adev->dm.compressor; in amdgpu_dm_fbc_init()
941 if (adev->dm.dc->fbc_compressor == NULL) in amdgpu_dm_fbc_init()
962 DRM_ERROR("DM: Failed to initialize FBC\n"); in amdgpu_dm_fbc_init()
964 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; in amdgpu_dm_fbc_init()
965 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); in amdgpu_dm_fbc_init()
985 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_audio_component_get_eld()
1005 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_audio_component_get_eld()
1025 adev->dm.audio_component = acomp; in amdgpu_dm_audio_component_bind()
1038 adev->dm.audio_component = NULL; in amdgpu_dm_audio_component_unbind()
1055 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; in amdgpu_dm_audio_init()
1065 adev->dm.dc->res_pool->audios[i]->inst; in amdgpu_dm_audio_init()
1073 adev->dm.audio_registered = true; in amdgpu_dm_audio_init()
1086 if (adev->dm.audio_registered) { in amdgpu_dm_audio_fini()
1088 adev->dm.audio_registered = false; in amdgpu_dm_audio_fini()
1098 struct drm_audio_component *acomp = adev->dm.audio_component; in amdgpu_dm_audio_eld_notify()
1111 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; in dm_dmub_hw_init()
1112 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; in dm_dmub_hw_init()
1113 const struct firmware *dmub_fw = adev->dm.dmub_fw; in dm_dmub_hw_init()
1114 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; in dm_dmub_hw_init()
1115 struct abm *abm = adev->dm.dc->res_pool->abm; in dm_dmub_hw_init()
1116 struct dc_context *ctx = adev->dm.dc->ctx; in dm_dmub_hw_init()
1222 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; in dm_dmub_hw_init()
1245 if (!adev->dm.dc->ctx->dmub_srv) in dm_dmub_hw_init()
1246 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); in dm_dmub_hw_init()
1247 if (!adev->dm.dc->ctx->dmub_srv) { in dm_dmub_hw_init()
1253 adev->dm.dmcub_fw_version); in dm_dmub_hw_init()
1260 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; in dm_dmub_hw_resume()
1419 mutex_lock(&adev->dm.dc_lock); in dm_handle_hpd_rx_offload_work()
1463 mutex_unlock(&adev->dm.dc_lock); in dm_handle_hpd_rx_offload_work()
1595 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) in retrieve_dmi_info() argument
1599 dm->aux_hpd_discon_quirk = false; in retrieve_dmi_info()
1603 dm->aux_hpd_discon_quirk = true; in retrieve_dmi_info()
1614 adev->dm.ddev = adev_to_drm(adev); in amdgpu_dm_init()
1615 adev->dm.adev = adev; in amdgpu_dm_init()
1621 mutex_init(&adev->dm.dpia_aux_lock); in amdgpu_dm_init()
1622 mutex_init(&adev->dm.dc_lock); in amdgpu_dm_init()
1623 mutex_init(&adev->dm.audio_lock); in amdgpu_dm_init()
1626 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); in amdgpu_dm_init()
1643 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); in amdgpu_dm_init()
1645 if (!adev->dm.cgs_device) { in amdgpu_dm_init()
1650 init_data.cgs_device = adev->dm.cgs_device; in amdgpu_dm_init()
1656 switch (adev->dm.dmcub_fw_version) { in amdgpu_dm_init()
1731 INIT_LIST_HEAD(&adev->dm.da_list); in amdgpu_dm_init()
1733 retrieve_dmi_info(&adev->dm); in amdgpu_dm_init()
1736 adev->dm.dc = dc_create(&init_data); in amdgpu_dm_init()
1738 if (adev->dm.dc) { in amdgpu_dm_init()
1740 dce_version_to_string(adev->dm.dc->ctx->dce_version)); in amdgpu_dm_init()
1747 adev->dm.dc->debug.force_single_disp_pipe_split = false; in amdgpu_dm_init()
1748 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; in amdgpu_dm_init()
1752 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; in amdgpu_dm_init()
1754 adev->dm.dc->debug.disable_stutter = true; in amdgpu_dm_init()
1757 adev->dm.dc->debug.disable_stutter = true; in amdgpu_dm_init()
1760 adev->dm.dc->debug.disable_dsc = true; in amdgpu_dm_init()
1763 adev->dm.dc->debug.disable_clock_gate = true; in amdgpu_dm_init()
1766 adev->dm.dc->debug.force_subvp_mclk_switch = true; in amdgpu_dm_init()
1768 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; in amdgpu_dm_init()
1771 adev->dm.dc->debug.ignore_cable_id = true; in amdgpu_dm_init()
1773 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) in amdgpu_dm_init()
1782 dc_hardware_init(adev->dm.dc); in amdgpu_dm_init()
1784 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); in amdgpu_dm_init()
1785 if (!adev->dm.hpd_rx_offload_wq) { in amdgpu_dm_init()
1796 dc_setup_system_context(adev->dm.dc, &pa_config); in amdgpu_dm_init()
1799 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); in amdgpu_dm_init()
1800 if (!adev->dm.freesync_module) { in amdgpu_dm_init()
1805 adev->dm.freesync_module); in amdgpu_dm_init()
1809 if (adev->dm.dc->caps.max_links > 0) { in amdgpu_dm_init()
1810 adev->dm.vblank_control_workqueue = in amdgpu_dm_init()
1812 if (!adev->dm.vblank_control_workqueue) in amdgpu_dm_init()
1816 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { in amdgpu_dm_init()
1817 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); in amdgpu_dm_init()
1819 if (!adev->dm.hdcp_workqueue) in amdgpu_dm_init()
1822 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); in amdgpu_dm_init()
1824 dc_init_callbacks(adev->dm.dc, &init_params); in amdgpu_dm_init()
1826 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { in amdgpu_dm_init()
1827 init_completion(&adev->dm.dmub_aux_transfer_done); in amdgpu_dm_init()
1828 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); in amdgpu_dm_init()
1829 if (!adev->dm.dmub_notify) { in amdgpu_dm_init()
1830 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); in amdgpu_dm_init()
1834 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); in amdgpu_dm_init()
1835 if (!adev->dm.delayed_hpd_wq) { in amdgpu_dm_init()
1852 dc_enable_dmub_outbox(adev->dm.dc); in amdgpu_dm_init()
1856 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); in amdgpu_dm_init()
1871 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_init()
1872 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_init()
1874 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { in amdgpu_dm_init()
1881 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); in amdgpu_dm_init()
1882 if (!adev->dm.secure_display_ctxs) in amdgpu_dm_init()
1908 if (adev->dm.vblank_control_workqueue) { in amdgpu_dm_fini()
1909 destroy_workqueue(adev->dm.vblank_control_workqueue); in amdgpu_dm_fini()
1910 adev->dm.vblank_control_workqueue = NULL; in amdgpu_dm_fini()
1913 amdgpu_dm_destroy_drm_device(&adev->dm); in amdgpu_dm_fini()
1916 if (adev->dm.secure_display_ctxs) { in amdgpu_dm_fini()
1918 if (adev->dm.secure_display_ctxs[i].crtc) { in amdgpu_dm_fini()
1919 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); in amdgpu_dm_fini()
1920 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); in amdgpu_dm_fini()
1923 kfree(adev->dm.secure_display_ctxs); in amdgpu_dm_fini()
1924 adev->dm.secure_display_ctxs = NULL; in amdgpu_dm_fini()
1927 if (adev->dm.hdcp_workqueue) { in amdgpu_dm_fini()
1928 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); in amdgpu_dm_fini()
1929 adev->dm.hdcp_workqueue = NULL; in amdgpu_dm_fini()
1932 if (adev->dm.dc) in amdgpu_dm_fini()
1933 dc_deinit_callbacks(adev->dm.dc); in amdgpu_dm_fini()
1935 if (adev->dm.dc) in amdgpu_dm_fini()
1936 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); in amdgpu_dm_fini()
1938 if (dc_enable_dmub_notifications(adev->dm.dc)) { in amdgpu_dm_fini()
1939 kfree(adev->dm.dmub_notify); in amdgpu_dm_fini()
1940 adev->dm.dmub_notify = NULL; in amdgpu_dm_fini()
1941 destroy_workqueue(adev->dm.delayed_hpd_wq); in amdgpu_dm_fini()
1942 adev->dm.delayed_hpd_wq = NULL; in amdgpu_dm_fini()
1945 if (adev->dm.dmub_bo) in amdgpu_dm_fini()
1946 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, in amdgpu_dm_fini()
1947 &adev->dm.dmub_bo_gpu_addr, in amdgpu_dm_fini()
1948 &adev->dm.dmub_bo_cpu_addr); in amdgpu_dm_fini()
1950 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { in amdgpu_dm_fini()
1951 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { in amdgpu_dm_fini()
1952 if (adev->dm.hpd_rx_offload_wq[i].wq) { in amdgpu_dm_fini()
1953 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); in amdgpu_dm_fini()
1954 adev->dm.hpd_rx_offload_wq[i].wq = NULL; in amdgpu_dm_fini()
1958 kfree(adev->dm.hpd_rx_offload_wq); in amdgpu_dm_fini()
1959 adev->dm.hpd_rx_offload_wq = NULL; in amdgpu_dm_fini()
1963 if (adev->dm.dc) in amdgpu_dm_fini()
1964 dc_destroy(&adev->dm.dc); in amdgpu_dm_fini()
1971 if (adev->dm.cgs_device) { in amdgpu_dm_fini()
1972 amdgpu_cgs_destroy_device(adev->dm.cgs_device); in amdgpu_dm_fini()
1973 adev->dm.cgs_device = NULL; in amdgpu_dm_fini()
1975 if (adev->dm.freesync_module) { in amdgpu_dm_fini()
1976 mod_freesync_destroy(adev->dm.freesync_module); in amdgpu_dm_fini()
1977 adev->dm.freesync_module = NULL; in amdgpu_dm_fini()
1980 mutex_destroy(&adev->dm.audio_lock); in amdgpu_dm_fini()
1981 mutex_destroy(&adev->dm.dc_lock); in amdgpu_dm_fini()
1982 mutex_destroy(&adev->dm.dpia_aux_lock); in amdgpu_dm_fini()
2053 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); in load_dmcu_fw()
2057 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); in load_dmcu_fw()
2060 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); in load_dmcu_fw()
2061 adev->dm.fw_dmcu = NULL; in load_dmcu_fw()
2067 amdgpu_ucode_release(&adev->dm.fw_dmcu); in load_dmcu_fw()
2071 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; in load_dmcu_fw()
2073 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; in load_dmcu_fw()
2078 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; in load_dmcu_fw()
2082 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); in load_dmcu_fw()
2093 return dm_read_reg(adev->dm.dc->ctx, address); in amdgpu_dm_dmub_reg_read()
2101 return dm_write_reg(adev->dm.dc->ctx, address, value); in amdgpu_dm_dmub_reg_write()
2160 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; in dm_dmub_sw_init()
2161 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); in dm_dmub_sw_init()
2167 adev->dm.dmub_fw; in dm_dmub_sw_init()
2172 adev->dm.dmcub_fw_version); in dm_dmub_sw_init()
2176 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); in dm_dmub_sw_init()
2177 dmub_srv = adev->dm.dmub_srv; in dm_dmub_sw_init()
2205 adev->dm.dmub_fw->data + in dm_dmub_sw_init()
2209 adev->dm.dmub_fw->data + in dm_dmub_sw_init()
2229 &adev->dm.dmub_bo, in dm_dmub_sw_init()
2230 &adev->dm.dmub_bo_gpu_addr, in dm_dmub_sw_init()
2231 &adev->dm.dmub_bo_cpu_addr); in dm_dmub_sw_init()
2237 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; in dm_dmub_sw_init()
2238 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; in dm_dmub_sw_init()
2241 adev->dm.dmub_fb_info = in dm_dmub_sw_init()
2242 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); in dm_dmub_sw_init()
2243 fb_info = adev->dm.dmub_fb_info; in dm_dmub_sw_init()
2276 kfree(adev->dm.dmub_fb_info); in dm_sw_fini()
2277 adev->dm.dmub_fb_info = NULL; in dm_sw_fini()
2279 if (adev->dm.dmub_srv) { in dm_sw_fini()
2280 dmub_srv_destroy(adev->dm.dmub_srv); in dm_sw_fini()
2281 kfree(adev->dm.dmub_srv); in dm_sw_fini()
2282 adev->dm.dmub_srv = NULL; in dm_sw_fini()
2285 amdgpu_ucode_release(&adev->dm.dmub_fw); in dm_sw_fini()
2286 amdgpu_ucode_release(&adev->dm.fw_dmcu); in dm_sw_fini()
2336 dmcu = adev->dm.dc->res_pool->dmcu; in dm_late_init()
2359 } else if (adev->dm.dc->ctx->dmub_srv) { in dm_late_init()
2363 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); in dm_late_init()
2365 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) in dm_late_init()
2521 * the initializers of each DM component, then populating the struct with them.
2580 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; in dm_gpureset_toggle_interrupts()
2598 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) in dm_gpureset_toggle_interrupts()
2647 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) in hpd_rx_irq_work_suspend() argument
2651 if (dm->hpd_rx_offload_wq) { in hpd_rx_irq_work_suspend()
2652 for (i = 0; i < dm->dc->caps.max_links; i++) in hpd_rx_irq_work_suspend()
2653 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); in hpd_rx_irq_work_suspend()
2660 struct amdgpu_display_manager *dm = &adev->dm; in dm_suspend() local
2664 mutex_lock(&dm->dc_lock); in dm_suspend()
2666 dc_allow_idle_optimizations(adev->dm.dc, false); in dm_suspend()
2668 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); in dm_suspend()
2670 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); in dm_suspend()
2672 amdgpu_dm_commit_zero_streams(dm->dc); in dm_suspend()
2676 hpd_rx_irq_work_suspend(dm); in dm_suspend()
2681 WARN_ON(adev->dm.cached_state); in dm_suspend()
2682 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); in dm_suspend()
2683 if (IS_ERR(adev->dm.cached_state)) in dm_suspend()
2684 return PTR_ERR(adev->dm.cached_state); in dm_suspend()
2690 hpd_rx_irq_work_suspend(dm); in dm_suspend()
2692 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); in dm_suspend()
2693 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); in dm_suspend()
2801 struct amdgpu_display_manager *dm) in dm_gpureset_commit_state() argument
2815 drm_err(dm->ddev, "Failed to allocate update bundle\n"); in dm_gpureset_commit_state()
2829 update_planes_and_stream_adapter(dm->dc, in dm_gpureset_commit_state()
2845 struct amdgpu_display_manager *dm = &adev->dm; in dm_resume() local
2855 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); in dm_resume()
2861 if (dm->dc->caps.ips_support) { in dm_resume()
2862 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); in dm_resume()
2866 dc_state = dm->cached_dc_state; in dm_resume()
2869 * The dc->current_state is backed up into dm->cached_dc_state in dm_resume()
2883 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); in dm_resume()
2889 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
2890 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
2892 dc_resume(dm->dc); in dm_resume()
2904 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { in dm_resume()
2906 dc_enable_dmub_outbox(adev->dm.dc); in dm_resume()
2909 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); in dm_resume()
2911 dm_gpureset_commit_state(dm->cached_dc_state, dm); in dm_resume()
2913 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); in dm_resume()
2915 dc_state_release(dm->cached_dc_state); in dm_resume()
2916 dm->cached_dc_state = NULL; in dm_resume()
2920 mutex_unlock(&dm->dc_lock); in dm_resume()
2926 dm_state->context = dc_state_create(dm->dc); in dm_resume()
2933 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { in dm_resume()
2935 dc_enable_dmub_outbox(adev->dm.dc); in dm_resume()
2939 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
2940 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
2943 dc_resume(dm->dc); in dm_resume()
2980 mutex_lock(&dm->dc_lock); in dm_resume()
2982 mutex_unlock(&dm->dc_lock); in dm_resume()
2997 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) in dm_resume()
3005 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { in dm_resume()
3014 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { in dm_resume()
3023 drm_atomic_helper_resume(ddev, dm->cached_state); in dm_resume()
3025 dm->cached_state = NULL; in dm_resume()
3056 * DOC: DM Lifecycle
3058 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3059 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3066 .name = "dm",
3125 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; in update_connector_ext_caps()
3312 if (adev->dm.disable_hpd_irq) in handle_hpd_irq_helper()
3321 if (adev->dm.hdcp_workqueue) { in handle_hpd_irq_helper()
3322 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); in handle_hpd_irq_helper()
3343 mutex_lock(&adev->dm.dc_lock); in handle_hpd_irq_helper()
3345 mutex_unlock(&adev->dm.dc_lock); in handle_hpd_irq_helper()
3402 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; in handle_hpd_rx_irq()
3406 if (adev->dm.disable_hpd_irq) in handle_hpd_rx_irq()
3491 mutex_lock(&adev->dm.dc_lock); in handle_hpd_rx_irq()
3493 mutex_unlock(&adev->dm.dc_lock); in handle_hpd_rx_irq()
3510 if (adev->dm.hdcp_workqueue) in handle_hpd_rx_irq()
3511 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); in handle_hpd_rx_irq()
3531 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { in register_hpd_handlers()
3574 struct dc *dc = adev->dm.dc; in dce60_register_irq_handlers()
3608 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dce60_register_irq_handlers()
3630 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dce60_register_irq_handlers()
3657 struct dc *dc = adev->dm.dc; in dce110_register_irq_handlers()
3694 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dce110_register_irq_handlers()
3715 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; in dce110_register_irq_handlers()
3737 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dce110_register_irq_handlers()
3763 struct dc *dc = adev->dm.dc; in dcn10_register_irq_handlers()
3809 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dcn10_register_irq_handlers()
3838 c_irq_params = &adev->dm.vline0_params[int_params.irq_source in dcn10_register_irq_handlers()
3868 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; in dcn10_register_irq_handlers()
3891 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dcn10_register_irq_handlers()
3916 struct dc *dc = adev->dm.dc; in register_outbox_irq_handlers()
3937 c_irq_params = &adev->dm.dmub_outbox_params[0]; in register_outbox_irq_handlers()
3960 struct amdgpu_display_manager *dm = &adev->dm; in dm_atomic_get_state() local
3966 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); in dm_atomic_get_state()
3980 struct amdgpu_display_manager *dm = &adev->dm; in dm_atomic_get_new_state() local
3986 if (obj->funcs == dm->atomic_obj.funcs) in dm_atomic_get_new_state()
4059 state->context = dc_state_create_current_copy(adev->dm.dc); in amdgpu_dm_mode_config_init()
4066 &adev->dm.atomic_obj, in amdgpu_dm_mode_config_init()
4096 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, in amdgpu_dm_update_backlight_caps() argument
4104 if (dm->backlight_caps[bl_idx].caps_valid) in amdgpu_dm_update_backlight_caps()
4109 dm->backlight_caps[bl_idx].caps_valid = true; in amdgpu_dm_update_backlight_caps()
4112 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; in amdgpu_dm_update_backlight_caps()
4113 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; in amdgpu_dm_update_backlight_caps()
4115 dm->backlight_caps[bl_idx].min_input_signal = in amdgpu_dm_update_backlight_caps()
4117 dm->backlight_caps[bl_idx].max_input_signal = in amdgpu_dm_update_backlight_caps()
4121 if (dm->backlight_caps[bl_idx].aux_support) in amdgpu_dm_update_backlight_caps()
4124 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; in amdgpu_dm_update_backlight_caps()
4125 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; in amdgpu_dm_update_backlight_caps()
4175 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, in amdgpu_dm_backlight_set_level() argument
4184 amdgpu_dm_update_backlight_caps(dm, bl_idx); in amdgpu_dm_backlight_set_level()
4185 caps = dm->backlight_caps[bl_idx]; in amdgpu_dm_backlight_set_level()
4187 dm->brightness[bl_idx] = user_brightness; in amdgpu_dm_backlight_set_level()
4190 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); in amdgpu_dm_backlight_set_level()
4191 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); in amdgpu_dm_backlight_set_level()
4192 link = (struct dc_link *)dm->backlight_link[bl_idx]; in amdgpu_dm_backlight_set_level()
4199 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); in amdgpu_dm_backlight_set_level()
4203 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); in amdgpu_dm_backlight_set_level()
4207 dm->actual_brightness[bl_idx] = user_brightness; in amdgpu_dm_backlight_set_level()
4212 struct amdgpu_display_manager *dm = bl_get_data(bd); in amdgpu_dm_backlight_update_status() local
4215 for (i = 0; i < dm->num_of_edps; i++) { in amdgpu_dm_backlight_update_status()
4216 if (bd == dm->backlight_dev[i]) in amdgpu_dm_backlight_update_status()
4221 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); in amdgpu_dm_backlight_update_status()
4226 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, in amdgpu_dm_backlight_get_level() argument
4231 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; in amdgpu_dm_backlight_get_level()
4233 amdgpu_dm_update_backlight_caps(dm, bl_idx); in amdgpu_dm_backlight_get_level()
4234 caps = dm->backlight_caps[bl_idx]; in amdgpu_dm_backlight_get_level()
4242 return dm->brightness[bl_idx]; in amdgpu_dm_backlight_get_level()
4249 return dm->brightness[bl_idx]; in amdgpu_dm_backlight_get_level()
4256 struct amdgpu_display_manager *dm = bl_get_data(bd); in amdgpu_dm_backlight_get_brightness() local
4259 for (i = 0; i < dm->num_of_edps; i++) { in amdgpu_dm_backlight_get_brightness()
4260 if (bd == dm->backlight_dev[i]) in amdgpu_dm_backlight_get_brightness()
4265 return amdgpu_dm_backlight_get_level(dm, i); in amdgpu_dm_backlight_get_brightness()
4278 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; in amdgpu_dm_register_backlight_device() local
4286 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); in amdgpu_dm_register_backlight_device()
4299 dm->backlight_dev[aconnector->bl_idx] = in amdgpu_dm_register_backlight_device()
4300 backlight_device_register(bl_name, aconnector->base.kdev, dm, in amdgpu_dm_register_backlight_device()
4303 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { in amdgpu_dm_register_backlight_device()
4304 DRM_ERROR("DM: Backlight registration failed!\n"); in amdgpu_dm_register_backlight_device()
4305 dm->backlight_dev[aconnector->bl_idx] = NULL; in amdgpu_dm_register_backlight_device()
4307 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); in amdgpu_dm_register_backlight_device()
4310 static int initialize_plane(struct amdgpu_display_manager *dm, in initialize_plane() argument
4333 if (plane_id >= dm->dc->caps.max_streams) in initialize_plane()
4336 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); in initialize_plane()
4351 static void setup_backlight_device(struct amdgpu_display_manager *dm, in setup_backlight_device() argument
4355 int bl_idx = dm->num_of_edps; in setup_backlight_device()
4361 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { in setup_backlight_device()
4362 …drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional… in setup_backlight_device()
4368 amdgpu_dm_update_backlight_caps(dm, bl_idx); in setup_backlight_device()
4369 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; in setup_backlight_device()
4370 dm->backlight_link[bl_idx] = link; in setup_backlight_device()
4371 dm->num_of_edps++; in setup_backlight_device()
4388 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_initialize_drm_device() local
4398 int max_overlay = dm->dc->caps.max_slave_planes; in amdgpu_dm_initialize_drm_device()
4400 dm->display_indexes_num = dm->dc->caps.max_streams; in amdgpu_dm_initialize_drm_device()
4402 adev->mode_info.num_crtc = adev->dm.display_indexes_num; in amdgpu_dm_initialize_drm_device()
4406 link_cnt = dm->dc->caps.max_links; in amdgpu_dm_initialize_drm_device()
4407 if (amdgpu_dm_mode_config_init(dm->adev)) { in amdgpu_dm_initialize_drm_device()
4408 DRM_ERROR("DM: Failed to initialize mode config\n"); in amdgpu_dm_initialize_drm_device()
4413 primary_planes = dm->dc->caps.max_streams; in amdgpu_dm_initialize_drm_device()
4421 plane = &dm->dc->caps.planes[i]; in amdgpu_dm_initialize_drm_device()
4423 if (initialize_plane(dm, mode_info, i, in amdgpu_dm_initialize_drm_device()
4439 for (i = 0; i < dm->dc->caps.max_planes; ++i) { in amdgpu_dm_initialize_drm_device()
4440 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; in amdgpu_dm_initialize_drm_device()
4455 if (initialize_plane(dm, NULL, primary_planes + i, in amdgpu_dm_initialize_drm_device()
4462 for (i = 0; i < dm->dc->caps.max_streams; i++) in amdgpu_dm_initialize_drm_device()
4463 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { in amdgpu_dm_initialize_drm_device()
4480 if (register_outbox_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
4481 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
4520 link = dc_get_link_at_index(dm->dc, i); in amdgpu_dm_initialize_drm_device()
4530 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { in amdgpu_dm_initialize_drm_device()
4550 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { in amdgpu_dm_initialize_drm_device()
4555 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { in amdgpu_dm_initialize_drm_device()
4560 if (dm->hpd_rx_offload_wq) in amdgpu_dm_initialize_drm_device()
4561 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = in amdgpu_dm_initialize_drm_device()
4573 mutex_lock(&dm->dc_lock); in amdgpu_dm_initialize_drm_device()
4575 mutex_unlock(&dm->dc_lock); in amdgpu_dm_initialize_drm_device()
4579 setup_backlight_device(dm, aconnector); in amdgpu_dm_initialize_drm_device()
4601 if (dce60_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
4602 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
4623 if (dce110_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
4624 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
4648 if (dcn10_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
4649 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
4669 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) in amdgpu_dm_destroy_drm_device() argument
4671 drm_atomic_private_obj_fini(&dm->atomic_obj); in amdgpu_dm_destroy_drm_device()
4785 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); in dm_init_microcode()
4797 /* if there is no object header, skip DM */ in dm_early_init()
4800 dev_info(adev->dev, "No object header, skipping DM\n"); in dm_early_init()
6423 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_connector_destroy() local
6433 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); in amdgpu_dm_connector_destroy()
6434 dm->backlight_dev[aconnector->bl_idx] = NULL; in amdgpu_dm_connector_destroy()
6742 dc_result = dc_validate_stream(adev->dm.dc, stream); in create_validate_stream_for_sink()
6747 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); in create_validate_stream_for_sink()
7475 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, in amdgpu_dm_connector_init_helper() argument
7481 struct amdgpu_device *adev = drm_to_adev(dm->ddev); in amdgpu_dm_connector_init_helper()
7531 dm->ddev->mode_config.scaling_mode_property, in amdgpu_dm_connector_init_helper()
7551 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { in amdgpu_dm_connector_init_helper()
7578 if (adev->dm.hdcp_workqueue) in amdgpu_dm_connector_init_helper()
7645 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); in create_i2c()
7657 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, in amdgpu_dm_connector_init() argument
7664 struct dc *dc = dm->dc; in amdgpu_dm_connector_init()
7689 dm->ddev, in amdgpu_dm_connector_init()
7706 dm, in amdgpu_dm_connector_init()
7717 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); in amdgpu_dm_connector_init()
7993 struct amdgpu_display_manager *dm, in update_freesync_state_on_stream() argument
8001 struct amdgpu_device *adev = dm->adev; in update_freesync_state_on_stream()
8024 dm->freesync_module, in update_freesync_state_on_stream()
8032 mod_freesync_handle_v_update(dm->freesync_module, in update_freesync_state_on_stream()
8036 dc_stream_adjust_vmin_vmax(dm->dc, in update_freesync_state_on_stream()
8059 dm->freesync_module, in update_freesync_state_on_stream()
8088 struct amdgpu_display_manager *dm, in update_stream_irq_parameters() argument
8094 struct amdgpu_device *adev = dm->adev; in update_stream_irq_parameters()
8134 mod_freesync_build_vrr_params(dm->freesync_module, in update_stream_irq_parameters()
8139 /* Copy state for access from DM IRQ handler */ in update_stream_irq_parameters()
8200 struct amdgpu_display_manager *dm, in amdgpu_dm_commit_planes() argument
8285 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, in amdgpu_dm_commit_planes()
8301 dm->adev, new_plane_state, in amdgpu_dm_commit_planes()
8335 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8340 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8377 dm, in amdgpu_dm_commit_planes()
8422 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, in amdgpu_dm_commit_planes()
8476 if (dm->vblank_control_workqueue) in amdgpu_dm_commit_planes()
8477 flush_workqueue(dm->vblank_control_workqueue); in amdgpu_dm_commit_planes()
8506 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8510 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8520 dm->dc, acrtc_state->stream, in amdgpu_dm_commit_planes()
8524 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8525 update_planes_and_stream_adapter(dm->dc, in amdgpu_dm_commit_planes()
8587 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_planes()
8639 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
8642 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
8674 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
8677 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
8697 static void dm_clear_writeback(struct amdgpu_display_manager *dm, in dm_clear_writeback() argument
8700 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); in dm_clear_writeback()
8708 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_commit_streams() local
8740 dm_clear_writeback(dm, dm_old_crtc_state); in amdgpu_dm_commit_streams()
8782 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_streams()
8784 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_streams()
8843 if (dm->vblank_control_workqueue) in amdgpu_dm_commit_streams()
8844 flush_workqueue(dm->vblank_control_workqueue); in amdgpu_dm_commit_streams()
8846 amdgpu_dm_psr_disable_all(dm); in amdgpu_dm_commit_streams()
8850 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_streams()
8851 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); in amdgpu_dm_commit_streams()
8854 if (dm->active_vblank_irq_count == 0) in amdgpu_dm_commit_streams()
8855 dc_allow_idle_optimizations(dm->dc, true); in amdgpu_dm_commit_streams()
8856 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_streams()
8880 static void dm_set_writeback(struct amdgpu_display_manager *dm, in dm_set_writeback() argument
8886 struct amdgpu_device *adev = dm->adev; in dm_set_writeback()
8914 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { in dm_set_writeback()
8915 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; in dm_set_writeback()
8972 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); in dm_set_writeback()
8980 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8991 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_atomic_commit_tail() local
9006 if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed) in amdgpu_dm_atomic_commit_tail()
9007 dc_allow_idle_optimizations(dm->dc, false); in amdgpu_dm_atomic_commit_tail()
9028 if (!adev->dm.hdcp_workqueue) in amdgpu_dm_atomic_commit_tail()
9079 if (!adev->dm.hdcp_workqueue) in amdgpu_dm_atomic_commit_tail()
9094 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); in amdgpu_dm_atomic_commit_tail()
9101 old_con_state, connector, adev->dm.hdcp_workqueue)) { in amdgpu_dm_atomic_commit_tail()
9118 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; in amdgpu_dm_atomic_commit_tail()
9135 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, in amdgpu_dm_atomic_commit_tail()
9218 mutex_lock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
9219 dc_update_planes_and_stream(dm->dc, in amdgpu_dm_atomic_commit_tail()
9224 mutex_unlock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
9247 update_stream_irq_parameters(dm, dm_new_crtc_state); in amdgpu_dm_atomic_commit_tail()
9304 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); in amdgpu_dm_atomic_commit_tail()
9328 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); in amdgpu_dm_atomic_commit_tail()
9336 for (i = 0; i < dm->num_of_edps; i++) { in amdgpu_dm_atomic_commit_tail()
9337 if (dm->backlight_dev[i] && in amdgpu_dm_atomic_commit_tail()
9338 (dm->actual_brightness[i] != dm->brightness[i])) in amdgpu_dm_atomic_commit_tail()
9339 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); in amdgpu_dm_atomic_commit_tail()
9625 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, in dm_update_crtc_state() argument
9700 dm->force_timing_sync; in dm_update_crtc_state()
9790 dm->dc, in dm_update_crtc_state()
9833 dm->dc, in dm_update_crtc_state()
10411 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10428 * Note that DM adds the affected connectors for all CRTCs in state, when that
10440 struct dc *dc = adev->dm.dc; in amdgpu_dm_atomic_check()
10600 ret = dm_update_crtc_state(&adev->dm, state, crtc, in amdgpu_dm_atomic_check()
10613 ret = dm_update_crtc_state(&adev->dm, state, crtc, in amdgpu_dm_atomic_check()
10739 * TODO: Remove this stall and drop DM state private objects. in amdgpu_dm_atomic_check()
10793 * the DM atomic state from validation we need to free it and in amdgpu_dm_atomic_check()
10796 * Furthermore, since the DM atomic state only contains the DC in amdgpu_dm_atomic_check()
10805 if (obj->funcs == adev->dm.atomic_obj.funcs) { in amdgpu_dm_atomic_check()
10890 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, in dm_edid_parser_send_cea() argument
10918 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); in dm_edid_parser_send_cea()
10947 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, in parse_edid_cea_dmcu() argument
10959 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) in parse_edid_cea_dmcu()
10966 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); in parse_edid_cea_dmcu()
10980 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); in parse_edid_cea_dmcu()
10988 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, in parse_edid_cea_dmub() argument
10997 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) in parse_edid_cea_dmub()
11011 mutex_lock(&adev->dm.dc_lock); in parse_edid_cea()
11012 if (adev->dm.dmub_srv) in parse_edid_cea()
11013 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); in parse_edid_cea()
11015 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); in parse_edid_cea()
11016 mutex_unlock(&adev->dm.dc_lock); in parse_edid_cea()
11138 if (!adev->dm.freesync_module) in amdgpu_dm_update_freesync_caps()
11147 adev->dm.dc, in amdgpu_dm_update_freesync_caps()
11254 struct dc *dc = adev->dm.dc; in amdgpu_dm_trigger_timing_sync()
11257 mutex_lock(&adev->dm.dc_lock); in amdgpu_dm_trigger_timing_sync()
11262 adev->dm.force_timing_sync; in amdgpu_dm_trigger_timing_sync()
11267 mutex_unlock(&adev->dm.dc_lock); in amdgpu_dm_trigger_timing_sync()
11317 struct dmub_notification *p_notify = adev->dm.dmub_notify; in amdgpu_dm_process_dmub_aux_transfer_sync()
11320 mutex_lock(&adev->dm.dpia_aux_lock); in amdgpu_dm_process_dmub_aux_transfer_sync()
11326 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { in amdgpu_dm_process_dmub_aux_transfer_sync()
11347 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; in amdgpu_dm_process_dmub_aux_transfer_sync()
11367 reinit_completion(&adev->dm.dmub_aux_transfer_done); in amdgpu_dm_process_dmub_aux_transfer_sync()
11368 mutex_unlock(&adev->dm.dpia_aux_lock); in amdgpu_dm_process_dmub_aux_transfer_sync()
11382 mutex_lock(&adev->dm.dpia_aux_lock); in amdgpu_dm_process_dmub_set_config_sync()
11384 link_index, payload, adev->dm.dmub_notify); in amdgpu_dm_process_dmub_set_config_sync()
11386 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { in amdgpu_dm_process_dmub_set_config_sync()
11388 *operation_result = adev->dm.dmub_notify->sc_status; in amdgpu_dm_process_dmub_set_config_sync()
11396 reinit_completion(&adev->dm.dmub_aux_transfer_done); in amdgpu_dm_process_dmub_set_config_sync()
11397 mutex_unlock(&adev->dm.dpia_aux_lock); in amdgpu_dm_process_dmub_set_config_sync()