amd/amdkfd/kfd_flat_memory.c

96  * The GPUVM_Base/GPUVM_Limit defines the aperture in the 64b space where we
114  * this case the GPUVM aperture (red) is defined and if a pointer falls in this
115  * aperture, we subtract the GPUVM_Base address and set the ATC bit to zero
149  * “Spare” aperture (APE1)
151  * We use the GPUVM aperture to differentiate ATC vs. GPUVM, but we also use
153  * config tables for setting cache policies. The “spare” (APE1) aperture is
155  * The default aperture isn’t an actual base/limit aperture; it is just the
162  * General Aperture definitions and rules
164  * An aperture register definition consists of a Base, Limit, Mtype, and
165  * usually an ATC bit indicating which translation tables that aperture uses.
166  * In all cases (for SUA and DUA apertures discussed later), aperture base
173  * The base and limit are considered inclusive to an aperture so being
174  * inside an aperture means (address >= Base) AND (address <= Limit).
177  * For example a load_dword_x4 that starts in one aperture and ends in another,
194  * space (defined by the aperture) for S_LOAD and FLAT_* ops.
195  * There is no spare (APE1) aperture for HSA32 mode.
201  * the default aperture is GPUVM (ATC==0) and not ATC space.
215  * the base/limit is “in” the aperture. For both HSA64 and GPUVM SUA modes,
226  * that fall in the private aperture are expanded as a function of the
229  * or ATC space. The addresses that fall in the shared aperture are
248  * Aperture Definitions for SUA and DUA
250  * The interpretation of the aperture register definitions for a given
301  * The aperture sizes are still 4GB implicitly.
303  * A GPUVM aperture is not applicable on GFXv9.
308 /* User mode manages most of the SVM aperture address space. The low
320 	 * aperture shouldn't be 0  in kfd_init_apertures_vi()
325 	/* dGPUs: SVM aperture starting at 0  in kfd_init_apertures_vi()