43 	base = vpe->ring.adev->reg_offset[VPE_HWIP][0][0];  in vpe_v6_1_get_reg_offset()
48 static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)  in vpe_v6_1_halt()  argument
50 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v6_1_halt()
54 	f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);  in vpe_v6_1_halt()
55 	f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0);  in vpe_v6_1_halt()
66 				&adev->vpe.trap_irq);  in vpe_v6_1_irq_init()
75 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v6_1_load_microcode()
87 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {  in vpe_v6_1_load_microcode()
92 		f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);  in vpe_v6_1_load_microcode()
95 		adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;  in vpe_v6_1_load_microcode()
96 		adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;  in vpe_v6_1_load_microcode()
106 	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;  in vpe_v6_1_load_microcode()
109 	ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);  in vpe_v6_1_load_microcode()
110 	ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);  in vpe_v6_1_load_microcode()
112 	ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset);  in vpe_v6_1_load_microcode()
113 	ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);  in vpe_v6_1_load_microcode()
123 		data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);  in vpe_v6_1_load_microcode()
126 		while (size_dw--) {  in vpe_v6_1_load_microcode()
143 	struct amdgpu_ring *ring = &vpe->ring;  in vpe_v6_1_ring_start()
144 	struct amdgpu_device *adev = ring->adev;  in vpe_v6_1_ring_start()
150 	rb_bufsz = order_base_2(ring->ring_size / 4);  in vpe_v6_1_ring_start()
163 	       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);  in vpe_v6_1_ring_start()
165 	       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);  in vpe_v6_1_ring_start()
167 	WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);  in vpe_v6_1_ring_start()
168 	WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);  in vpe_v6_1_ring_start()
170 	ring->wptr = 0;  in vpe_v6_1_ring_start()
175 	WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);  in vpe_v6_1_ring_start()
176 	WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);  in vpe_v6_1_ring_start()
184 	doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);  in vpe_v6_1_ring_start()
185 …doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbe…  in vpe_v6_1_ring_start()
190 	adev->nbio.funcs->vpe_doorbell_range(adev, 0, ring->use_doorbell, ring->doorbell_index, 2);  in vpe_v6_1_ring_start()
200 	ring->sched.ready = true;  in vpe_v6_1_ring_start()
204 		ring->sched.ready = false;  in vpe_v6_1_ring_start()
213 	struct amdgpu_device *adev = vpe->ring.adev;  in vpe_v_6_1_ring_stop()
224 		dev_err(adev->dev, "VPE queue reset failed\n");  in vpe_v_6_1_ring_stop()
226 	vpe->ring.sched.ready = false;  in vpe_v_6_1_ring_stop()
236 	struct amdgpu_vpe *vpe = &adev->vpe;  in vpe_v6_1_set_trap_irq_state()
252 	dev_dbg(adev->dev, "IH: VPE trap\n");  in vpe_v6_1_process_trap_irq()
254 	switch (entry->client_id) {  in vpe_v6_1_process_trap_irq()
256 		amdgpu_fence_process(&adev->vpe.ring);  in vpe_v6_1_process_trap_irq()
267 	vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;  in vpe_v6_1_set_regs()
268 	vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;  in vpe_v6_1_set_regs()
269 	vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;  in vpe_v6_1_set_regs()
270 	vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;  in vpe_v6_1_set_regs()
271 	vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;  in vpe_v6_1_set_regs()
273 	vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;  in vpe_v6_1_set_regs()
274 	vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;  in vpe_v6_1_set_regs()
275 	vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;  in vpe_v6_1_set_regs()
276 	vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;  in vpe_v6_1_set_regs()
277 	vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;  in vpe_v6_1_set_regs()
278 	vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;  in vpe_v6_1_set_regs()
279 	vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;  in vpe_v6_1_set_regs()
280 	vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;  in vpe_v6_1_set_regs()
304 	vpe->funcs = &vpe_v6_1_funcs;  in vpe_v6_1_set_funcs()
305 	vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;  in vpe_v6_1_set_funcs()