Lines Matching full:indirect
437 * @indirect: indirectly write sram
441 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
450 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
458 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
461 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
463 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
465 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
471 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
474 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
478 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
481 if (!indirect) in vcn_v4_0_mc_resume_dpg_mode()
483 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
486 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
489 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
495 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
497 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
500 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
502 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
504 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
507 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
512 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
515 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
517 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
519 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
524 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
527 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
529 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
532 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
536 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
776 * @indirect: indirectly write sram
781 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode() argument
812 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
816 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
820 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
824 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
887 bool indirect) in vcn_v4_0_enable_ras() argument
900 tmp, 0, indirect); in vcn_v4_0_enable_ras()
905 tmp, 0, indirect); in vcn_v4_0_enable_ras()
913 * @indirect: indirectly write sram
917 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_start_dpg_mode() argument
932 if (indirect) in vcn_v4_0_start_dpg_mode()
936 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); in vcn_v4_0_start_dpg_mode()
942 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
946 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_start_dpg_mode()
958 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
962 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v4_0_start_dpg_mode()
969 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
976 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
982 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
984 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); in vcn_v4_0_start_dpg_mode()
989 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
994 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
996 vcn_v4_0_enable_ras(adev, inst_idx, indirect); in vcn_v4_0_start_dpg_mode()
1001 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v4_0_start_dpg_mode()
1004 if (indirect) in vcn_v4_0_start_dpg_mode()