243 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_init_microcode()
401 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_insert_nop()  local
405 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_insert_nop()
562 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_stop()
621 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_ctx_switch_enable()
663 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_enable()
690 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_resume()
691 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_gfx_resume()
845  * sdma_v5_0_load_microcode - load the sDMA ME ucode
862 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_load_microcode()
863 		if (!adev->sdma.instance[i].fw)  in sdma_v5_0_load_microcode()
866 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v5_0_load_microcode()
871 			(adev->sdma.instance[i].fw->data +  in sdma_v5_0_load_microcode()
882 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v5_0_load_microcode()
917 	/* enable sdma ring preemption */  in sdma_v5_0_start()
1153  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1181  * Update PTEs by writing them manually using sDMA (NAVI10).
1202  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1211  * Update the page tables using sDMA (NAVI10).
1240 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_pad_ib()  local
1246 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_pad_ib()
1283  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1290  * using sDMA (NAVI10).
1356 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1359 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1363 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1366 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1370 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_sw_init()
1371 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_sw_init()
1375 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,  in sdma_v5_0_sw_init()
1383 		sprintf(ring->name, "sdma%d", i);  in sdma_v5_0_sw_init()
1384 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,  in sdma_v5_0_sw_init()
1400 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v5_0_sw_fini()
1401 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v5_0_sw_fini()
1452 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_is_idle()
1560 	DRM_DEBUG("IH: SDMA trap\n");  in sdma_v5_0_process_trap_irq()
1581 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v5_0_process_trap_irq()
1597 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v5_0_process_trap_irq()
1627 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_clock_gating()
1629 			/* Enable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1642 			/* Disable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1664 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_light_sleep()
1666 			/* Enable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1673 			/* Disable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1791 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_ring_funcs()
1792 		adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;  in sdma_v5_0_set_ring_funcs()
1793 		adev->sdma.instance[i].ring.me = i;  in sdma_v5_0_set_ring_funcs()
1808 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v5_0_set_irq_funcs()
1809 					adev->sdma.num_instances;  in sdma_v5_0_set_irq_funcs()
1810 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1811 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1815  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1845  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1880 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v5_0_set_buffer_funcs()
1897 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_vm_pte_funcs()
1899 				&adev->sdma.instance[i].ring.sched;  in sdma_v5_0_set_vm_pte_funcs()
1901 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v5_0_set_vm_pte_funcs()