Lines Matching +full:32 +full:- +full:bits
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
73 … volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
108 /* PSP boot config sub-commands */
125 …uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary…
126 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
128 …uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (m…
129 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
151 …uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must b…
152 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
185 …uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must b…
186 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
190 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/
196 …uint32_t system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer…
197 …uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffe…
204 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
205 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
206 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
207 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
208 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
209 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
210 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
211 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
214 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
215 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
226 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
227 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
235 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
284 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */
306 …uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (m…
307 …uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
317 …uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as …
318 …uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as…
332 …uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must…
333 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
341 …enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process com…
343 …uint32_t boot_config_valid; /* dynamic boot configuration valid bits bit…
374 /* Command-specific response for Fw Attestation Db */
381 /* Command-specific response for boot config. */
386 /* Union of command-specific responses for GPCOM ring. */
401 …uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw co…
402 …uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw c…
407 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */
423 …uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (…
424 …uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer …
430 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
437 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
448 …uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must …
449 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
451 …uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame …
452 …uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame…
454 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
455 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
456 …uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame…