Lines Matching +full:disable +full:- +full:eop
51 struct amdgpu_device *adev = ring->adev; in mes_v10_1_ring_set_wptr()
53 if (ring->use_doorbell) { in mes_v10_1_ring_set_wptr()
54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, in mes_v10_1_ring_set_wptr()
55 ring->wptr); in mes_v10_1_ring_set_wptr()
56 WDOORBELL64(ring->doorbell_index, ring->wptr); in mes_v10_1_ring_set_wptr()
64 return *ring->rptr_cpu_addr; in mes_v10_1_ring_get_rptr()
71 if (ring->use_doorbell) in mes_v10_1_ring_get_wptr()
72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); in mes_v10_1_ring_get_wptr()
97 struct amdgpu_device *adev = mes->adev; in mes_v10_1_submit_pkt_and_poll_completion()
98 struct amdgpu_ring *ring = &mes->ring; in mes_v10_1_submit_pkt_and_poll_completion()
103 spin_lock_irqsave(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
105 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
106 return -ENOMEM; in mes_v10_1_submit_pkt_and_poll_completion()
110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; in mes_v10_1_submit_pkt_and_poll_completion()
111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; in mes_v10_1_submit_pkt_and_poll_completion()
115 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
117 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); in mes_v10_1_submit_pkt_and_poll_completion()
119 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, in mes_v10_1_submit_pkt_and_poll_completion()
120 adev->usec_timeout); in mes_v10_1_submit_pkt_and_poll_completion()
123 x_pkt->header.opcode); in mes_v10_1_submit_pkt_and_poll_completion()
128 return -ETIMEDOUT; in mes_v10_1_submit_pkt_and_poll_completion()
144 return -1; in convert_to_mes_queue_type()
150 struct amdgpu_device *adev = mes->adev; in mes_v10_1_add_hw_queue()
152 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; in mes_v10_1_add_hw_queue()
153 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; in mes_v10_1_add_hw_queue()
161 mes_add_queue_pkt.process_id = input->process_id; in mes_v10_1_add_hw_queue()
162 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; in mes_v10_1_add_hw_queue()
163 mes_add_queue_pkt.process_va_start = input->process_va_start; in mes_v10_1_add_hw_queue()
164 mes_add_queue_pkt.process_va_end = input->process_va_end; in mes_v10_1_add_hw_queue()
165 mes_add_queue_pkt.process_quantum = input->process_quantum; in mes_v10_1_add_hw_queue()
166 mes_add_queue_pkt.process_context_addr = input->process_context_addr; in mes_v10_1_add_hw_queue()
167 mes_add_queue_pkt.gang_quantum = input->gang_quantum; in mes_v10_1_add_hw_queue()
168 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; in mes_v10_1_add_hw_queue()
170 input->inprocess_gang_priority; in mes_v10_1_add_hw_queue()
172 input->gang_global_priority_level; in mes_v10_1_add_hw_queue()
173 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; in mes_v10_1_add_hw_queue()
174 mes_add_queue_pkt.mqd_addr = input->mqd_addr; in mes_v10_1_add_hw_queue()
175 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v10_1_add_hw_queue()
177 convert_to_mes_queue_type(input->queue_type); in mes_v10_1_add_hw_queue()
178 mes_add_queue_pkt.paging = input->paging; in mes_v10_1_add_hw_queue()
180 mes_add_queue_pkt.gws_base = input->gws_base; in mes_v10_1_add_hw_queue()
181 mes_add_queue_pkt.gws_size = input->gws_size; in mes_v10_1_add_hw_queue()
182 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; in mes_v10_1_add_hw_queue()
200 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; in mes_v10_1_remove_hw_queue()
201 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; in mes_v10_1_remove_hw_queue()
219 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; in mes_v10_1_unmap_legacy_queue()
222 mes_remove_queue_pkt.pipe_id = input->pipe_id; in mes_v10_1_unmap_legacy_queue()
223 mes_remove_queue_pkt.queue_id = input->queue_id; in mes_v10_1_unmap_legacy_queue()
225 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { in mes_v10_1_unmap_legacy_queue()
227 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; in mes_v10_1_unmap_legacy_queue()
229 lower_32_bits(input->trail_fence_data); in mes_v10_1_unmap_legacy_queue()
231 if (input->queue_type == AMDGPU_RING_TYPE_GFX) in mes_v10_1_unmap_legacy_queue()
272 struct amdgpu_device *adev = mes->adev; in mes_v10_1_set_hw_resources()
281 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v10_1_set_hw_resources()
282 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v10_1_set_hw_resources()
283 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; in mes_v10_1_set_hw_resources()
285 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; in mes_v10_1_set_hw_resources()
287 mes->query_status_fence_gpu_addr; in mes_v10_1_set_hw_resources()
291 mes->compute_hqd_mask[i]; in mes_v10_1_set_hw_resources()
294 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; in mes_v10_1_set_hw_resources()
297 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; in mes_v10_1_set_hw_resources()
301 mes->aggregated_doorbells[i]; in mes_v10_1_set_hw_resources()
304 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v10_1_set_hw_resources()
306 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v10_1_set_hw_resources()
308 adev->reg_offset[OSSSYS_HWIP][0][i]; in mes_v10_1_set_hw_resources()
322 struct amdgpu_device *adev = mes->adev; in mes_v10_1_init_aggregated_doorbell()
329 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << in mes_v10_1_init_aggregated_doorbell()
338 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << in mes_v10_1_init_aggregated_doorbell()
347 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << in mes_v10_1_init_aggregated_doorbell()
356 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << in mes_v10_1_init_aggregated_doorbell()
365 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << in mes_v10_1_init_aggregated_doorbell()
391 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_buffer()
393 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_buffer()
394 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); in mes_v10_1_allocate_ucode_buffer()
395 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); in mes_v10_1_allocate_ucode_buffer()
399 &adev->mes.ucode_fw_obj[pipe], in mes_v10_1_allocate_ucode_buffer()
400 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_buffer()
401 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_buffer()
403 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); in mes_v10_1_allocate_ucode_buffer()
407 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_buffer()
409 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
410 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
424 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_data_buffer()
426 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_data_buffer()
427 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); in mes_v10_1_allocate_ucode_data_buffer()
428 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); in mes_v10_1_allocate_ucode_data_buffer()
432 &adev->mes.data_fw_obj[pipe], in mes_v10_1_allocate_ucode_data_buffer()
433 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_data_buffer()
434 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
436 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); in mes_v10_1_allocate_ucode_data_buffer()
440 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_data_buffer()
442 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
443 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
451 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
452 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
453 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
455 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
456 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
457 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
468 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); in mes_v10_1_enable()
471 mutex_lock(&adev->srbm_mutex); in mes_v10_1_enable()
473 if (!adev->enable_mes_kiq && in mes_v10_1_enable()
479 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_enable()
482 mutex_unlock(&adev->srbm_mutex); in mes_v10_1_enable()
493 adev->enable_mes_kiq ? 1 : 0); in mes_v10_1_enable()
504 adev->enable_mes_kiq ? 1 : 0); in mes_v10_1_enable()
519 if (!adev->mes.fw[pipe]) in mes_v10_1_load_microcode()
520 return -EINVAL; in mes_v10_1_load_microcode()
534 mutex_lock(&adev->srbm_mutex); in mes_v10_1_load_microcode()
540 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_load_microcode()
544 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
546 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
548 /* set ucode instruction cache boundary to 2M-1 */ in mes_v10_1_load_microcode()
553 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
555 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
557 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ in mes_v10_1_load_microcode()
600 mutex_unlock(&adev->srbm_mutex); in mes_v10_1_load_microcode()
609 u32 *eop; in mes_v10_1_allocate_eop_buf() local
613 &adev->mes.eop_gpu_obj[pipe], in mes_v10_1_allocate_eop_buf()
614 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_allocate_eop_buf()
615 (void **)&eop); in mes_v10_1_allocate_eop_buf()
617 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); in mes_v10_1_allocate_eop_buf()
621 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size); in mes_v10_1_allocate_eop_buf()
623 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
624 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
631 struct v10_compute_mqd *mqd = ring->mqd_ptr; in mes_v10_1_mqd_init()
637 mqd->header = 0xC0310800; in mes_v10_1_mqd_init()
638 mqd->compute_pipelinestat_enable = 0x00000001; in mes_v10_1_mqd_init()
639 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in mes_v10_1_mqd_init()
640 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in mes_v10_1_mqd_init()
641 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in mes_v10_1_mqd_init()
642 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in mes_v10_1_mqd_init()
643 mqd->compute_misc_reserved = 0x00000003; in mes_v10_1_mqd_init()
645 eop_base_addr = ring->eop_gpu_addr >> 8; in mes_v10_1_mqd_init()
647 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ in mes_v10_1_mqd_init()
650 (order_base_2(MES_EOP_SIZE / 4) - 1)); in mes_v10_1_mqd_init()
652 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); in mes_v10_1_mqd_init()
653 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in mes_v10_1_mqd_init()
654 mqd->cp_hqd_eop_control = tmp; in mes_v10_1_mqd_init()
656 /* disable the queue if it's active */ in mes_v10_1_mqd_init()
657 ring->wptr = 0; in mes_v10_1_mqd_init()
658 mqd->cp_hqd_pq_rptr = 0; in mes_v10_1_mqd_init()
659 mqd->cp_hqd_pq_wptr_lo = 0; in mes_v10_1_mqd_init()
660 mqd->cp_hqd_pq_wptr_hi = 0; in mes_v10_1_mqd_init()
663 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in mes_v10_1_mqd_init()
664 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v10_1_mqd_init()
669 mqd->cp_mqd_control = tmp; in mes_v10_1_mqd_init()
672 hqd_gpu_addr = ring->gpu_addr >> 8; in mes_v10_1_mqd_init()
673 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v10_1_mqd_init()
674 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v10_1_mqd_init()
677 wb_gpu_addr = ring->rptr_gpu_addr; in mes_v10_1_mqd_init()
678 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v10_1_mqd_init()
679 mqd->cp_hqd_pq_rptr_report_addr_hi = in mes_v10_1_mqd_init()
683 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v10_1_mqd_init()
684 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v10_1_mqd_init()
685 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v10_1_mqd_init()
690 (order_base_2(ring->ring_size / 4) - 1)); in mes_v10_1_mqd_init()
692 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); in mes_v10_1_mqd_init()
701 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
705 if (ring->use_doorbell) { in mes_v10_1_mqd_init()
707 DOORBELL_OFFSET, ring->doorbell_index); in mes_v10_1_mqd_init()
718 mqd->cp_hqd_pq_doorbell_control = tmp; in mes_v10_1_mqd_init()
720 mqd->cp_hqd_vmid = 0; in mes_v10_1_mqd_init()
722 mqd->cp_hqd_active = 1; in mes_v10_1_mqd_init()
723 mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT; in mes_v10_1_mqd_init()
724 mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT; in mes_v10_1_mqd_init()
725 mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT; in mes_v10_1_mqd_init()
726 mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT; in mes_v10_1_mqd_init()
730 /* offset: 184 - this is used for CP_HQD_GFX_CONTROL */ in mes_v10_1_mqd_init()
731 mqd->cp_hqd_suspend_cntl_stack_offset = tmp; in mes_v10_1_mqd_init()
733 amdgpu_device_flush_hdp(ring->adev, NULL); in mes_v10_1_mqd_init()
740 struct v10_compute_mqd *mqd = ring->mqd_ptr;
741 struct amdgpu_device *adev = ring->adev;
744 mutex_lock(&adev->srbm_mutex);
745 nv_grbm_select(adev, 3, ring->pipe, 0, 0);
759 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
760 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
768 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
773 mqd->cp_hqd_pq_rptr_report_addr_lo);
775 mqd->cp_hqd_pq_rptr_report_addr_hi);
778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
782 mqd->cp_hqd_pq_wptr_poll_addr_lo);
784 mqd->cp_hqd_pq_wptr_poll_addr_hi);
788 mqd->cp_hqd_pq_doorbell_control);
791 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
794 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
797 mutex_unlock(&adev->srbm_mutex);
803 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v10_1_kiq_enable_queue()
804 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v10_1_kiq_enable_queue()
807 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v10_1_kiq_enable_queue()
808 return -EINVAL; in mes_v10_1_kiq_enable_queue()
810 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v10_1_kiq_enable_queue()
816 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
825 r = mes_v10_1_mqd_init(&adev->mes.ring); in mes_v10_1_queue_init()
840 ring = &adev->mes.ring; in mes_v10_1_ring_init()
842 ring->funcs = &mes_v10_1_ring_funcs; in mes_v10_1_ring_init()
844 ring->me = 3; in mes_v10_1_ring_init()
845 ring->pipe = 0; in mes_v10_1_ring_init()
846 ring->queue = 0; in mes_v10_1_ring_init()
848 ring->ring_obj = NULL; in mes_v10_1_ring_init()
849 ring->use_doorbell = true; in mes_v10_1_ring_init()
850 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; in mes_v10_1_ring_init()
851 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; in mes_v10_1_ring_init()
852 ring->no_scheduler = true; in mes_v10_1_ring_init()
853 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); in mes_v10_1_ring_init()
863 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v10_1_kiq_ring_init()
865 ring = &adev->gfx.kiq[0].ring; in mes_v10_1_kiq_ring_init()
867 ring->me = 3; in mes_v10_1_kiq_ring_init()
868 ring->pipe = 1; in mes_v10_1_kiq_ring_init()
869 ring->queue = 0; in mes_v10_1_kiq_ring_init()
871 ring->adev = NULL; in mes_v10_1_kiq_ring_init()
872 ring->ring_obj = NULL; in mes_v10_1_kiq_ring_init()
873 ring->use_doorbell = true; in mes_v10_1_kiq_ring_init()
874 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; in mes_v10_1_kiq_ring_init()
875 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; in mes_v10_1_kiq_ring_init()
876 ring->no_scheduler = true; in mes_v10_1_kiq_ring_init()
877 sprintf(ring->name, "mes_kiq_%d.%d.%d", in mes_v10_1_kiq_ring_init()
878 ring->me, ring->pipe, ring->queue); in mes_v10_1_kiq_ring_init()
891 ring = &adev->gfx.kiq[0].ring; in mes_v10_1_mqd_sw_init()
893 ring = &adev->mes.ring; in mes_v10_1_mqd_sw_init()
897 if (ring->mqd_obj) in mes_v10_1_mqd_sw_init()
902 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, in mes_v10_1_mqd_sw_init()
903 &ring->mqd_gpu_addr, &ring->mqd_ptr); in mes_v10_1_mqd_sw_init()
905 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in mes_v10_1_mqd_sw_init()
908 memset(ring->mqd_ptr, 0, mqd_size); in mes_v10_1_mqd_sw_init()
911 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); in mes_v10_1_mqd_sw_init()
912 if (!adev->mes.mqd_backup[pipe]) { in mes_v10_1_mqd_sw_init()
913 dev_warn(adev->dev, in mes_v10_1_mqd_sw_init()
915 ring->name); in mes_v10_1_mqd_sw_init()
916 return -ENOMEM; in mes_v10_1_mqd_sw_init()
927 adev->mes.funcs = &mes_v10_1_funcs; in mes_v10_1_sw_init()
928 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; in mes_v10_1_sw_init()
935 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) in mes_v10_1_sw_init()
947 if (adev->enable_mes_kiq) { in mes_v10_1_sw_init()
965 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); in mes_v10_1_sw_fini()
966 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); in mes_v10_1_sw_fini()
969 kfree(adev->mes.mqd_backup[pipe]); in mes_v10_1_sw_fini()
971 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], in mes_v10_1_sw_fini()
972 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_sw_fini()
974 amdgpu_ucode_release(&adev->mes.fw[pipe]); in mes_v10_1_sw_fini()
977 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, in mes_v10_1_sw_fini()
978 &adev->gfx.kiq[0].ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
979 &adev->gfx.kiq[0].ring.mqd_ptr); in mes_v10_1_sw_fini()
981 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, in mes_v10_1_sw_fini()
982 &adev->mes.ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
983 &adev->mes.ring.mqd_ptr); in mes_v10_1_sw_fini()
985 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); in mes_v10_1_sw_fini()
986 amdgpu_ring_fini(&adev->mes.ring); in mes_v10_1_sw_fini()
995 struct amdgpu_device *adev = ring->adev; in mes_v10_1_kiq_setting()
1005 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); in mes_v10_1_kiq_setting()
1013 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); in mes_v10_1_kiq_setting()
1025 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { in mes_v10_1_kiq_hw_init()
1041 mes_v10_1_kiq_setting(&adev->gfx.kiq[0].ring); in mes_v10_1_kiq_hw_init()
1059 if (!adev->enable_mes_kiq) { in mes_v10_1_hw_init()
1060 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { in mes_v10_1_hw_init()
1076 r = mes_v10_1_set_hw_resources(&adev->mes); in mes_v10_1_hw_init()
1080 mes_v10_1_init_aggregated_doorbell(&adev->mes); in mes_v10_1_hw_init()
1082 r = mes_v10_1_query_sched_status(&adev->mes); in mes_v10_1_hw_init()
1089 * Disable KIQ ring usage from the driver once MES is enabled. in mes_v10_1_hw_init()
1093 adev->gfx.kiq[0].ring.sched.ready = false; in mes_v10_1_hw_init()
1094 adev->mes.ring.sched.ready = true; in mes_v10_1_hw_init()
1107 adev->mes.ring.sched.ready = false; in mes_v10_1_hw_fini()
1111 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { in mes_v10_1_hw_fini()
1149 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) in mes_v10_0_early_init()