Lines Matching full:jpeg
58 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
59 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
68 * jpeg_v4_0_5_sw_init - sw init for JPEG block
80 /* JPEG TRAP */ in jpeg_v4_0_5_sw_init()
82 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v4_0_5_sw_init()
86 /* JPEG DJPEG POISON EVENT */ in jpeg_v4_0_5_sw_init()
88 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq); in jpeg_v4_0_5_sw_init()
92 /* JPEG EJPEG POISON EVENT */ in jpeg_v4_0_5_sw_init()
94 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq); in jpeg_v4_0_5_sw_init()
106 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_5_sw_init()
114 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_5_sw_init()
119 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v4_0_5_sw_init()
120 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v4_0_5_sw_init()
126 * jpeg_v4_0_5_sw_fini - sw fini for JPEG block
130 * JPEG suspend and free up sw allocation
147 * jpeg_v4_0_5_hw_init - start and test JPEG block
155 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_5_hw_init()
162 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); in jpeg_v4_0_5_hw_init()
172 * Stop the JPEG block, mark ring as not ready any more
180 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v4_0_5_hw_fini()
181 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) in jpeg_v4_0_5_hw_fini()
189 * jpeg_v4_0_5_suspend - suspend JPEG block
193 * HW fini and suspend JPEG block
210 * jpeg_v4_0_5_resume - resume JPEG block
214 * Resume firmware and hw init JPEG block
234 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_5_disable_clock_gating()
244 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_disable_clock_gating()
246 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v4_0_5_disable_clock_gating()
251 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); in jpeg_v4_0_5_disable_clock_gating()
258 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_5_enable_clock_gating()
268 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v4_0_5_enable_clock_gating()
270 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v4_0_5_enable_clock_gating()
275 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); in jpeg_v4_0_5_enable_clock_gating()
281 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_disable_static_power_gating()
283 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_disable_static_power_gating()
288 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_5_disable_static_power_gating()
291 /* keep the JPEG in static PG mode */ in jpeg_v4_0_5_disable_static_power_gating()
292 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_5_disable_static_power_gating()
301 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), in jpeg_v4_0_5_enable_static_power_gating()
306 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_enable_static_power_gating()
308 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_enable_static_power_gating()
317 * jpeg_v4_0_5_start - start JPEG block
321 * Setup and start the JPEG block
325 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_5_start()
344 /* JPEG disable CGC */ in jpeg_v4_0_5_start()
348 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v4_0_5_start()
353 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, in jpeg_v4_0_5_start()
357 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), in jpeg_v4_0_5_start()
361 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v4_0_5_start()
362 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v4_0_5_start()
363 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v4_0_5_start()
365 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v4_0_5_start()
367 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); in jpeg_v4_0_5_start()
368 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); in jpeg_v4_0_5_start()
369 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v4_0_5_start()
370 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v4_0_5_start()
371 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start()
377 * jpeg_v4_0_5_stop - stop JPEG block
381 * stop the JPEG block
388 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), in jpeg_v4_0_5_stop()
416 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); in jpeg_v4_0_5_dec_ring_get_rptr()
433 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_dec_ring_get_wptr()
451 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v4_0_5_dec_ring_set_wptr()
460 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & in jpeg_v4_0_5_is_idle()
471 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v4_0_5_wait_for_idle()
500 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; in jpeg_v4_0_5_set_powergating_state()
504 if (state == adev->jpeg.cur_state) in jpeg_v4_0_5_set_powergating_state()
513 adev->jpeg.cur_state = state; in jpeg_v4_0_5_set_powergating_state()
522 DRM_DEBUG("IH: JPEG TRAP\n"); in jpeg_v4_0_5_process_interrupt()
526 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v4_0_5_process_interrupt()
592 adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs; in jpeg_v4_0_5_set_dec_ring_funcs()
593 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); in jpeg_v4_0_5_set_dec_ring_funcs()
602 adev->jpeg.inst->irq.num_types = 1; in jpeg_v4_0_5_set_irq_funcs()
603 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_5_irq_funcs; in jpeg_v4_0_5_set_irq_funcs()