Lines Matching +full:0 +full:x80004000
36 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
75 return 0; in jpeg_v4_0_3_early_init()
91 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
110 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
129 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
140 (j ? (0x40 * j - 0xc80) : 0)); in jpeg_v4_0_3_sw_init()
152 return 0; in jpeg_v4_0_3_sw_init()
191 direct_wt = { {0} }; in jpeg_v4_0_3_start_sriov()
192 struct mmsch_v4_0_cmd_end end = { {0} }; in jpeg_v4_0_3_start_sriov()
200 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v4_0_3_start_sriov()
203 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); in jpeg_v4_0_3_start_sriov()
212 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { in jpeg_v4_0_3_start_sriov()
214 table_size = 0; in jpeg_v4_0_3_start_sriov()
216 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); in jpeg_v4_0_3_start_sriov()
218 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); in jpeg_v4_0_3_start_sriov()
220 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); in jpeg_v4_0_3_start_sriov()
225 header.mjpegdec0[j].init_status = 0; in jpeg_v4_0_3_start_sriov()
229 header.mjpegdec1[j - 4].init_status = 0; in jpeg_v4_0_3_start_sriov()
249 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); in jpeg_v4_0_3_start_sriov()
255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_3_start_sriov()
257 param = 0x00000001; in jpeg_v4_0_3_start_sriov()
259 tmp = 0; in jpeg_v4_0_3_start_sriov()
261 resp = 0; in jpeg_v4_0_3_start_sriov()
268 if (resp != 0) in jpeg_v4_0_3_start_sriov()
275 "(expected=0x%08x, readback=0x%08x)\n", in jpeg_v4_0_3_start_sriov()
282 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", in jpeg_v4_0_3_start_sriov()
286 return 0; in jpeg_v4_0_3_start_sriov()
306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v4_0_3_hw_init()
307 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
309 ring->wptr = 0; in jpeg_v4_0_3_hw_init()
310 ring->wptr_old = 0; in jpeg_v4_0_3_hw_init()
316 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_hw_init()
328 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_hw_init()
334 (ring->pipe ? (ring->pipe - 0x15) : 0), in jpeg_v4_0_3_hw_init()
346 return 0; in jpeg_v4_0_3_hw_init()
359 int ret = 0; in jpeg_v4_0_3_hw_fini()
433 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_disable_clock_gating()
458 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) in jpeg_v4_0_3_enable_clock_gating()
475 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_start()
489 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); in jpeg_v4_0_3_start()
501 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, in jpeg_v4_0_3_start()
504 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_start()
505 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_start()
517 reg_offset, 0); in jpeg_v4_0_3_start()
521 (0x00000001L | 0x00000002L)); in jpeg_v4_0_3_start()
532 reg_offset, 0); in jpeg_v4_0_3_start()
535 reg_offset, 0); in jpeg_v4_0_3_start()
538 reg_offset, 0x00000002L); in jpeg_v4_0_3_start()
548 return 0; in jpeg_v4_0_3_start()
562 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_stop()
586 return 0; in jpeg_v4_0_3_stop()
602 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_rptr()
622 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); in jpeg_v4_0_3_dec_ring_get_wptr()
642 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : in jpeg_v4_0_3_dec_ring_set_wptr()
643 0), in jpeg_v4_0_3_dec_ring_set_wptr()
659 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_start()
660 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v4_0_3_dec_ring_insert_start()
664 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_start()
665 amdgpu_ring_write(ring, 0x80004000); in jpeg_v4_0_3_dec_ring_insert_start()
679 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_end()
680 amdgpu_ring_write(ring, 0x62a04); in jpeg_v4_0_3_dec_ring_insert_end()
684 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_insert_end()
685 amdgpu_ring_write(ring, 0x00004000); in jpeg_v4_0_3_dec_ring_insert_end()
704 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
708 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
712 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
716 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
720 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
721 amdgpu_ring_write(ring, 0x8); in jpeg_v4_0_3_dec_ring_emit_fence()
724 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); in jpeg_v4_0_3_dec_ring_emit_fence()
725 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
729 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
730 amdgpu_ring_write(ring, 0x4); in jpeg_v4_0_3_dec_ring_emit_fence()
732 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
733 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
737 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
738 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v4_0_3_dec_ring_emit_fence()
742 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
743 amdgpu_ring_write(ring, 0x0); in jpeg_v4_0_3_dec_ring_emit_fence()
745 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_emit_fence()
746 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
750 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_fence()
751 amdgpu_ring_write(ring, 0x1); in jpeg_v4_0_3_dec_ring_emit_fence()
753 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v4_0_3_dec_ring_emit_fence()
754 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_fence()
775 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
779 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
783 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
787 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
791 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
795 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
799 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
802 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v4_0_3_dec_ring_emit_ib()
803 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_ib()
806 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
807 amdgpu_ring_write(ring, 0x01400200); in jpeg_v4_0_3_dec_ring_emit_ib()
810 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_ib()
811 amdgpu_ring_write(ring, 0x2); in jpeg_v4_0_3_dec_ring_emit_ib()
814 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_ib()
815 amdgpu_ring_write(ring, 0x2); in jpeg_v4_0_3_dec_ring_emit_ib()
824 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
825 amdgpu_ring_write(ring, 0x01400200); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
828 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
832 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
833 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v4_0_3_dec_ring_emit_reg_wait()
834 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
836 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
840 0, 0, PACKETJ_TYPE3)); in jpeg_v4_0_3_dec_ring_emit_reg_wait()
856 mask = 0xffffffff; in jpeg_v4_0_3_dec_ring_emit_vm_flush()
865 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
866 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v4_0_3_dec_ring_emit_wreg()
867 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_emit_wreg()
869 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
873 0, 0, PACKETJ_TYPE0)); in jpeg_v4_0_3_dec_ring_emit_wreg()
884 for (i = 0; i < count / 2; i++) { in jpeg_v4_0_3_dec_ring_nop()
885 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v4_0_3_dec_ring_nop()
886 amdgpu_ring_write(ring, 0); in jpeg_v4_0_3_dec_ring_nop()
896 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_is_idle()
897 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_is_idle()
898 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_is_idle()
915 int ret = 0; in jpeg_v4_0_3_wait_for_idle()
918 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_wait_for_idle()
919 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_wait_for_idle()
920 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_wait_for_idle()
939 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_clockgating_state()
948 return 0; in jpeg_v4_0_3_set_clockgating_state()
959 return 0; in jpeg_v4_0_3_set_powergating_state()
963 return 0; in jpeg_v4_0_3_set_powergating_state()
981 return 0; in jpeg_v4_0_3_set_interrupt_state()
993 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) in jpeg_v4_0_3_process_interrupt()
1001 return 0; in jpeg_v4_0_3_process_interrupt()
1006 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); in jpeg_v4_0_3_process_interrupt()
1031 entry->src_id, entry->src_data[0]); in jpeg_v4_0_3_process_interrupt()
1035 return 0; in jpeg_v4_0_3_process_interrupt()
1060 .align_mask = 0xf,
1091 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_dec_ring_funcs()
1092 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_set_dec_ring_funcs()
1113 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_set_irq_funcs()
1122 .minor = 0,
1128 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S),
1130 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D),
1132 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S),
1134 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D),
1136 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S),
1138 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D),
1140 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S),
1142 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D),
1144 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S),
1146 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D),
1148 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S),
1150 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D),
1152 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S),
1154 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D),
1156 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S),
1158 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D),
1172 NULL, 0, GET_INST(VCN, jpeg_inst), in jpeg_v4_0_3_inst_query_ras_error_count()
1187 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_query_ras_error_count()
1209 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) in jpeg_v4_0_3_reset_ras_error_count()