60 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v4_0_early_init()
61 	adev->jpeg.num_jpeg_rings = 1;  in jpeg_v4_0_early_init()
71  * jpeg_v4_0_sw_init - sw init for JPEG block
83 	/* JPEG TRAP */  in jpeg_v4_0_sw_init()
85 		VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v4_0_sw_init()
89 	/* JPEG DJPEG POISON EVENT */  in jpeg_v4_0_sw_init()
91 			VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);  in jpeg_v4_0_sw_init()
95 	/* JPEG EJPEG POISON EVENT */  in jpeg_v4_0_sw_init()
97 			VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);  in jpeg_v4_0_sw_init()
109 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v4_0_sw_init()
115 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v4_0_sw_init()
120 	adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v4_0_sw_init()
121 	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);  in jpeg_v4_0_sw_init()
131  * jpeg_v4_0_sw_fini - sw fini for JPEG block
135  * JPEG suspend and free up sw allocation
152  * jpeg_v4_0_hw_init - start and test JPEG block
160 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v4_0_hw_init()
184 	DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");  in jpeg_v4_0_hw_init()
194  * Stop the JPEG block, mark ring as not ready any more
202 		if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v4_0_hw_fini()
203 			RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))  in jpeg_v4_0_hw_fini()
207 		amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);  in jpeg_v4_0_hw_fini()
213  * jpeg_v4_0_suspend - suspend JPEG block
217  * HW fini and suspend JPEG block
234  * jpeg_v4_0_resume - resume JPEG block
238  * Resume firmware and hw init JPEG block
258 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);  in jpeg_v4_0_disable_clock_gating()
268 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_disable_clock_gating()
270 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);  in jpeg_v4_0_disable_clock_gating()
275 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);  in jpeg_v4_0_disable_clock_gating()
282 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);  in jpeg_v4_0_enable_clock_gating()
292 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_enable_clock_gating()
294 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);  in jpeg_v4_0_enable_clock_gating()
299 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);  in jpeg_v4_0_enable_clock_gating()
309 		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);  in jpeg_v4_0_disable_static_power_gating()
311 		r = SOC15_WAIT_ON_RREG(JPEG, 0,  in jpeg_v4_0_disable_static_power_gating()
316 			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n");  in jpeg_v4_0_disable_static_power_gating()
322 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,  in jpeg_v4_0_disable_static_power_gating()
325 	/* keep the JPEG in static PG mode */  in jpeg_v4_0_disable_static_power_gating()
326 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,  in jpeg_v4_0_disable_static_power_gating()
335 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),  in jpeg_v4_0_enable_static_power_gating()
344 		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);  in jpeg_v4_0_enable_static_power_gating()
346 		r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,  in jpeg_v4_0_enable_static_power_gating()
351 			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n");  in jpeg_v4_0_enable_static_power_gating()
360  * jpeg_v4_0_start - start JPEG block
364  * Setup and start the JPEG block
368 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v4_0_start()
379 	/* JPEG disable CGC */  in jpeg_v4_0_start()
383 	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,  in jpeg_v4_0_start()
388 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,  in jpeg_v4_0_start()
392 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),  in jpeg_v4_0_start()
396 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);  in jpeg_v4_0_start()
397 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));  in jpeg_v4_0_start()
398 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,  in jpeg_v4_0_start()
400 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,  in jpeg_v4_0_start()
402 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);  in jpeg_v4_0_start()
403 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);  in jpeg_v4_0_start()
404 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);  in jpeg_v4_0_start()
405 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v4_0_start()
406 	ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);  in jpeg_v4_0_start()
450 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v4_0_start_sriov()
452 	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,  in jpeg_v4_0_start_sriov()
455 	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,  in jpeg_v4_0_start_sriov()
458 	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,  in jpeg_v4_0_start_sriov()
527 …DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", re…  in jpeg_v4_0_start_sriov()
536  * jpeg_v4_0_stop - stop JPEG block
540  * stop the JPEG block
547 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),  in jpeg_v4_0_stop()
575 	return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);  in jpeg_v4_0_dec_ring_get_rptr()
592 		return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);  in jpeg_v4_0_dec_ring_get_wptr()
610 		WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v4_0_dec_ring_set_wptr()
619 	ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &  in jpeg_v4_0_is_idle()
630 	return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,  in jpeg_v4_0_wait_for_idle()
659 		adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;  in jpeg_v4_0_set_powergating_state()
663 	if (state == adev->jpeg.cur_state)  in jpeg_v4_0_set_powergating_state()
672 		adev->jpeg.cur_state = state;  in jpeg_v4_0_set_powergating_state()
689 	DRM_DEBUG("IH: JPEG TRAP\n");  in jpeg_v4_0_process_interrupt()
693 		amdgpu_fence_process(adev->jpeg.inst->ring_dec);  in jpeg_v4_0_process_interrupt()
755 	adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs;  in jpeg_v4_0_set_dec_ring_funcs()
756 	DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");  in jpeg_v4_0_set_dec_ring_funcs()
770 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v4_0_set_irq_funcs()
771 	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;  in jpeg_v4_0_set_irq_funcs()
773 	adev->jpeg.inst->ras_poison_irq.num_types = 1;  in jpeg_v4_0_set_irq_funcs()
774 	adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;  in jpeg_v4_0_set_irq_funcs()
792 		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);  in jpeg_v4_0_query_poison_by_instance()
796 		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);  in jpeg_v4_0_query_poison_by_instance()
804 		dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",  in jpeg_v4_0_query_poison_by_instance()
814 	for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)  in jpeg_v4_0_query_ras_poison_status()
837 		adev->jpeg.ras = &jpeg_v4_0_ras;  in jpeg_v4_0_set_ras_funcs()