60 		harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);  in jpeg_v3_0_early_init()
66 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v3_0_early_init()
67 	adev->jpeg.num_jpeg_rings = 1;  in jpeg_v3_0_early_init()
76  * jpeg_v3_0_sw_init - sw init for JPEG block
88 	/* JPEG TRAP */  in jpeg_v3_0_sw_init()
90 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v3_0_sw_init()
102 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v3_0_sw_init()
107 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v3_0_sw_init()
112 	adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v3_0_sw_init()
113 	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);  in jpeg_v3_0_sw_init()
119  * jpeg_v3_0_sw_fini - sw fini for JPEG block
123  * JPEG suspend and free up sw allocation
140  * jpeg_v3_0_hw_init - start and test JPEG block
148 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v3_0_hw_init()
158 	DRM_INFO("JPEG decode initialized successfully.\n");  in jpeg_v3_0_hw_init()
168  * Stop the JPEG block, mark ring as not ready any more
176 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v3_0_hw_fini()
177 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))  in jpeg_v3_0_hw_fini()
184  * jpeg_v3_0_suspend - suspend JPEG block
188  * HW fini and suspend JPEG block
205  * jpeg_v3_0_resume - resume JPEG block
209  * Resume firmware and hw init JPEG block
229 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v3_0_disable_clock_gating()
237 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v3_0_disable_clock_gating()
239 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v3_0_disable_clock_gating()
245 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v3_0_disable_clock_gating()
247 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v3_0_disable_clock_gating()
252 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v3_0_disable_clock_gating()
259 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v3_0_enable_clock_gating()
265 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v3_0_enable_clock_gating()
275 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v3_0_disable_static_power_gating()
277 		r = SOC15_WAIT_ON_RREG(JPEG, 0,  in jpeg_v3_0_disable_static_power_gating()
282 			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");  in jpeg_v3_0_disable_static_power_gating()
288 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,  in jpeg_v3_0_disable_static_power_gating()
291 	/* keep the JPEG in static PG mode */  in jpeg_v3_0_disable_static_power_gating()
292 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,  in jpeg_v3_0_disable_static_power_gating()
301 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),  in jpeg_v3_0_enable_static_power_gating()
310 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v3_0_enable_static_power_gating()
312 		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,  in jpeg_v3_0_enable_static_power_gating()
317 			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");  in jpeg_v3_0_enable_static_power_gating()
326  * jpeg_v3_0_start - start JPEG block
330  * Setup and start the JPEG block
334 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v3_0_start()
345 	/* JPEG disable CGC */  in jpeg_v3_0_start()
349 	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,  in jpeg_v3_0_start()
351 	WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,  in jpeg_v3_0_start()
355 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,  in jpeg_v3_0_start()
359 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),  in jpeg_v3_0_start()
363 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);  in jpeg_v3_0_start()
364 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));  in jpeg_v3_0_start()
365 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,  in jpeg_v3_0_start()
367 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,  in jpeg_v3_0_start()
369 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);  in jpeg_v3_0_start()
370 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);  in jpeg_v3_0_start()
371 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);  in jpeg_v3_0_start()
372 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v3_0_start()
373 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v3_0_start()
379  * jpeg_v3_0_stop - stop JPEG block
383  * stop the JPEG block
390 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),  in jpeg_v3_0_stop()
418 	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);  in jpeg_v3_0_dec_ring_get_rptr()
435 		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v3_0_dec_ring_get_wptr()
453 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v3_0_dec_ring_set_wptr()
462 	ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &  in jpeg_v3_0_is_idle()
473 	return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,  in jpeg_v3_0_wait_for_idle()
501 	if(state == adev->jpeg.cur_state)  in jpeg_v3_0_set_powergating_state()
510 		adev->jpeg.cur_state = state;  in jpeg_v3_0_set_powergating_state()
527 	DRM_DEBUG("IH: JPEG TRAP\n");  in jpeg_v3_0_process_interrupt()
531 		amdgpu_fence_process(adev->jpeg.inst->ring_dec);  in jpeg_v3_0_process_interrupt()
593 	adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs;  in jpeg_v3_0_set_dec_ring_funcs()
594 	DRM_INFO("JPEG decode is enabled in VM mode\n");  in jpeg_v3_0_set_dec_ring_funcs()
604 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v3_0_set_irq_funcs()
605 	adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;  in jpeg_v3_0_set_irq_funcs()