Lines Matching full:jpeg
63 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_5_early_init()
64 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; in jpeg_v2_5_early_init()
65 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v2_5_early_init()
66 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); in jpeg_v2_5_early_init()
68 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
70 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | in jpeg_v2_5_early_init()
82 * jpeg_v2_5_sw_init - sw init for JPEG block
94 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
95 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
98 /* JPEG TRAP */ in jpeg_v2_5_sw_init()
100 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
104 /* JPEG DJPEG POISON EVENT */ in jpeg_v2_5_sw_init()
106 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
110 /* JPEG EJPEG POISON EVENT */ in jpeg_v2_5_sw_init()
112 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
125 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
126 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
129 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_sw_init()
137 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, in jpeg_v2_5_sw_init()
142 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_5_sw_init()
143 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); in jpeg_v2_5_sw_init()
154 * jpeg_v2_5_sw_fini - sw fini for JPEG block
158 * JPEG suspend and free up sw allocation
175 * jpeg_v2_5_hw_init - start and test JPEG block
186 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_hw_init()
187 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_init()
190 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_hw_init()
199 DRM_INFO("JPEG decode initialized successfully.\n"); in jpeg_v2_5_hw_init()
209 * Stop the JPEG block, mark ring as not ready any more
218 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_hw_fini()
219 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_fini()
222 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_5_hw_fini()
223 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) in jpeg_v2_5_hw_fini()
227 amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0); in jpeg_v2_5_hw_fini()
234 * jpeg_v2_5_suspend - suspend JPEG block
238 * HW fini and suspend JPEG block
255 * jpeg_v2_5_resume - resume JPEG block
259 * Resume firmware and hw init JPEG block
279 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
287 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
289 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
294 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_disable_clock_gating()
296 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
301 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
308 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
314 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_enable_clock_gating()
318 * jpeg_v2_5_start - start JPEG block
322 * Setup and start the JPEG block
329 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_start()
330 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_start()
333 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_start()
335 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v2_5_start()
338 /* JPEG disable CGC */ in jpeg_v2_5_start()
342 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, in jpeg_v2_5_start()
344 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v2_5_start()
348 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, in jpeg_v2_5_start()
352 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), in jpeg_v2_5_start()
356 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v2_5_start()
357 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_5_start()
358 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v2_5_start()
360 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v2_5_start()
362 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_5_start()
363 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_5_start()
364 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_5_start()
365 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_5_start()
366 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
373 * jpeg_v2_5_stop - stop JPEG block
377 * stop the JPEG block
383 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_stop()
384 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_stop()
388 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), in jpeg_v2_5_stop()
395 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), in jpeg_v2_5_stop()
414 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
431 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
449 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_5_dec_ring_set_wptr()
494 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_is_idle()
495 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_is_idle()
498 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & in jpeg_v2_5_is_idle()
511 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_wait_for_idle()
512 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_wait_for_idle()
515 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()
532 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_clockgating_state()
533 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_clockgating_state()
554 if(state == adev->jpeg.cur_state) in jpeg_v2_5_set_powergating_state()
563 adev->jpeg.cur_state = state; in jpeg_v2_5_set_powergating_state()
602 DRM_DEBUG("IH: JPEG TRAP\n"); in jpeg_v2_5_process_interrupt()
606 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec); in jpeg_v2_5_process_interrupt()
719 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_dec_ring_funcs()
720 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_dec_ring_funcs()
723 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs; in jpeg_v2_5_set_dec_ring_funcs()
725 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs; in jpeg_v2_5_set_dec_ring_funcs()
726 adev->jpeg.inst[i].ring_dec->me = i; in jpeg_v2_5_set_dec_ring_funcs()
727 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); in jpeg_v2_5_set_dec_ring_funcs()
745 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_irq_funcs()
746 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_irq_funcs()
749 adev->jpeg.inst[i].irq.num_types = 1; in jpeg_v2_5_set_irq_funcs()
750 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; in jpeg_v2_5_set_irq_funcs()
752 adev->jpeg.inst[i].ras_poison_irq.num_types = 1; in jpeg_v2_5_set_irq_funcs()
753 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs; in jpeg_v2_5_set_irq_funcs()
782 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS); in jpeg_v2_6_query_poison_by_instance()
786 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS); in jpeg_v2_6_query_poison_by_instance()
794 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", in jpeg_v2_6_query_poison_by_instance()
804 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) in jpeg_v2_6_query_ras_poison_status()
827 adev->jpeg.ras = &jpeg_v2_6_ras; in jpeg_v2_5_set_ras_funcs()