51 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v2_0_early_init()
52 	adev->jpeg.num_jpeg_rings = 1;  in jpeg_v2_0_early_init()
61  * jpeg_v2_0_sw_init - sw init for JPEG block
73 	/* JPEG TRAP */  in jpeg_v2_0_sw_init()
75 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v2_0_sw_init()
87 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_sw_init()
92 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,  in jpeg_v2_0_sw_init()
97 	adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v2_0_sw_init()
98 	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);  in jpeg_v2_0_sw_init()
104  * jpeg_v2_0_sw_fini - sw fini for JPEG block
108  * JPEG suspend and free up sw allocation
125  * jpeg_v2_0_hw_init - start and test JPEG block
133 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_hw_init()
141 		DRM_INFO("JPEG decode initialized successfully.\n");  in jpeg_v2_0_hw_init()
151  * Stop the JPEG block, mark ring as not ready any more
159 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v2_0_hw_fini()
160 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))  in jpeg_v2_0_hw_fini()
167  * jpeg_v2_0_suspend - suspend JPEG block
171  * HW fini and suspend JPEG block
188  * jpeg_v2_0_resume - resume JPEG block
192  * Resume firmware and hw init JPEG block
215 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v2_0_disable_power_gating()
217 		r = SOC15_WAIT_ON_RREG(JPEG, 0,  in jpeg_v2_0_disable_power_gating()
222 			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");  in jpeg_v2_0_disable_power_gating()
228 	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;  in jpeg_v2_0_disable_power_gating()
229 	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);  in jpeg_v2_0_disable_power_gating()
240 		data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));  in jpeg_v2_0_enable_power_gating()
243 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);  in jpeg_v2_0_enable_power_gating()
246 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v2_0_enable_power_gating()
248 		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,  in jpeg_v2_0_enable_power_gating()
253 			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");  in jpeg_v2_0_enable_power_gating()
265 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v2_0_disable_clock_gating()
273 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v2_0_disable_clock_gating()
275 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v2_0_disable_clock_gating()
281 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v2_0_disable_clock_gating()
288 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v2_0_enable_clock_gating()
296 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v2_0_enable_clock_gating()
298 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v2_0_enable_clock_gating()
304 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v2_0_enable_clock_gating()
308  * jpeg_v2_0_start - start JPEG block
312  * Setup and start the JPEG block
316 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_start()
327 	/* JPEG disable CGC */  in jpeg_v2_0_start()
330 	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in jpeg_v2_0_start()
333 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,  in jpeg_v2_0_start()
337 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),  in jpeg_v2_0_start()
341 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);  in jpeg_v2_0_start()
342 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));  in jpeg_v2_0_start()
343 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,  in jpeg_v2_0_start()
345 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,  in jpeg_v2_0_start()
347 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);  in jpeg_v2_0_start()
348 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);  in jpeg_v2_0_start()
349 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);  in jpeg_v2_0_start()
350 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v2_0_start()
351 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v2_0_start()
357  * jpeg_v2_0_stop - stop JPEG block
361  * stop the JPEG block
368 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),  in jpeg_v2_0_stop()
372 	/* enable JPEG CGC */  in jpeg_v2_0_stop()
397 	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);  in jpeg_v2_0_dec_ring_get_rptr()
414 		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v2_0_dec_ring_get_wptr()
432 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v2_0_dec_ring_set_wptr()
664 	return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &  in jpeg_v2_0_is_idle()
674 	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,  in jpeg_v2_0_wait_for_idle()
703 	if (state == adev->jpeg.cur_state)  in jpeg_v2_0_set_powergating_state()
712 		adev->jpeg.cur_state = state;  in jpeg_v2_0_set_powergating_state()
729 	DRM_DEBUG("IH: JPEG TRAP\n");  in jpeg_v2_0_process_interrupt()
733 		amdgpu_fence_process(adev->jpeg.inst->ring_dec);  in jpeg_v2_0_process_interrupt()
795 	adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;  in jpeg_v2_0_set_dec_ring_funcs()
796 	DRM_INFO("JPEG decode is enabled in VM mode\n");  in jpeg_v2_0_set_dec_ring_funcs()
806 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v2_0_set_irq_funcs()
807 	adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;  in jpeg_v2_0_set_irq_funcs()