Lines Matching +full:0 +full:x80010000
57 return 0; in jpeg_v2_0_early_init()
90 ring->vm_hub = AMDGPU_MMHUB0(0); in jpeg_v2_0_sw_init()
93 0, AMDGPU_RING_PRIO_DEFAULT, NULL); in jpeg_v2_0_sw_init()
97 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_0_sw_init()
98 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
100 return 0; in jpeg_v2_0_sw_init()
137 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); in jpeg_v2_0_hw_init()
160 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v2_0_hw_fini()
163 return 0; in jpeg_v2_0_hw_fini()
211 int r = 0; in jpeg_v2_0_disable_power_gating()
215 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_disable_power_gating()
217 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
228 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; in jpeg_v2_0_disable_power_gating()
229 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); in jpeg_v2_0_disable_power_gating()
231 return 0; in jpeg_v2_0_disable_power_gating()
238 int r = 0; in jpeg_v2_0_enable_power_gating()
240 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); in jpeg_v2_0_enable_power_gating()
242 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; in jpeg_v2_0_enable_power_gating()
243 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); in jpeg_v2_0_enable_power_gating()
246 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_enable_power_gating()
248 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
258 return 0; in jpeg_v2_0_enable_power_gating()
265 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_disable_clock_gating()
273 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_disable_clock_gating()
275 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_disable_clock_gating()
281 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_disable_clock_gating()
288 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_enable_clock_gating()
292 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in jpeg_v2_0_enable_clock_gating()
296 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_enable_clock_gating()
298 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_enable_clock_gating()
304 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_enable_clock_gating()
330 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in jpeg_v2_0_start()
333 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, in jpeg_v2_0_start()
337 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), in jpeg_v2_0_start()
341 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v2_0_start()
342 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_0_start()
343 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v2_0_start()
345 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v2_0_start()
347 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_0_start()
348 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_0_start()
349 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_0_start()
350 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
351 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
353 return 0; in jpeg_v2_0_start()
368 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), in jpeg_v2_0_stop()
383 return 0; in jpeg_v2_0_stop()
397 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v2_0_dec_ring_get_rptr()
414 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_dec_ring_get_wptr()
432 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
446 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_start()
447 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
450 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_start()
451 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
464 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_end()
465 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
468 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_insert_end()
469 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
488 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
492 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
496 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
500 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
504 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
505 amdgpu_ring_write(ring, 0x8); in jpeg_v2_0_dec_ring_emit_fence()
508 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); in jpeg_v2_0_dec_ring_emit_fence()
509 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
512 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
513 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v2_0_dec_ring_emit_fence()
516 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_fence()
517 amdgpu_ring_write(ring, 0x1); in jpeg_v2_0_dec_ring_emit_fence()
519 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
520 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
541 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
545 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
549 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
553 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
557 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
561 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
565 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
569 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
572 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v2_0_dec_ring_emit_ib()
573 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
576 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
577 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_ib()
580 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_ib()
581 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
584 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_ib()
585 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
594 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
595 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_reg_wait()
598 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
602 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_reg_wait()
603 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_reg_wait()
604 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_reg_wait()
606 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
610 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
626 mask = 0xffffffff; in jpeg_v2_0_dec_ring_emit_vm_flush()
635 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
636 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_wreg()
637 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_wreg()
639 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
643 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
654 for (i = 0; i < count / 2; i++) { in jpeg_v2_0_dec_ring_nop()
655 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v2_0_dec_ring_nop()
656 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_nop()
664 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v2_0_is_idle()
674 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
694 return 0; in jpeg_v2_0_set_clockgating_state()
704 return 0; in jpeg_v2_0_set_powergating_state()
722 return 0; in jpeg_v2_0_set_interrupt_state()
737 entry->src_id, entry->src_data[0]); in jpeg_v2_0_process_interrupt()
741 return 0; in jpeg_v2_0_process_interrupt()
766 .align_mask = 0xf,
813 .minor = 0,
814 .rev = 0,