Lines Matching +full:0 +full:x80010000
41 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACK… in jpeg_v1_0_decode_ring_patch_wreg()
42 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
43 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
44 ring->ring[(*ptr)++] = 0; in jpeg_v1_0_decode_ring_patch_wreg()
45 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
48 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
60 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); in jpeg_v1_0_decode_ring_set_patch_ring()
66 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); in jpeg_v1_0_decode_ring_set_patch_ring()
72 for (i = 0; i <= 2; i++) { in jpeg_v1_0_decode_ring_set_patch_ring()
73 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); in jpeg_v1_0_decode_ring_set_patch_ring()
74 ring->ring[ptr++] = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
78 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
80 val = 0x13; in jpeg_v1_0_decode_ring_set_patch_ring()
84 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); in jpeg_v1_0_decode_ring_set_patch_ring()
86 val = 0x1; in jpeg_v1_0_decode_ring_set_patch_ring()
90 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
92 val = 0x1; in jpeg_v1_0_decode_ring_set_patch_ring()
93 mask = 0x1; in jpeg_v1_0_decode_ring_set_patch_ring()
95 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_… in jpeg_v1_0_decode_ring_set_patch_ring()
96 ring->ring[ptr++] = 0x01400200; in jpeg_v1_0_decode_ring_set_patch_ring()
97 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0… in jpeg_v1_0_decode_ring_set_patch_ring()
99 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ… in jpeg_v1_0_decode_ring_set_patch_ring()
100 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_set_patch_ring()
101 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_set_patch_ring()
102 ring->ring[ptr++] = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
103 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); in jpeg_v1_0_decode_ring_set_patch_ring()
106 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); in jpeg_v1_0_decode_ring_set_patch_ring()
111 for (i = 0; i <= 12; i++) { in jpeg_v1_0_decode_ring_set_patch_ring()
112 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); in jpeg_v1_0_decode_ring_set_patch_ring()
113 ring->ring[ptr++] = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
117 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring()
119 val = 0; in jpeg_v1_0_decode_ring_set_patch_ring()
123 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
125 val = 0x12; in jpeg_v1_0_decode_ring_set_patch_ring()
140 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_get_rptr()
154 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_decode_ring_get_wptr()
168 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v1_0_decode_ring_set_wptr()
183 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
184 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
186 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
187 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
202 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
203 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
205 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
206 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
227 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
231 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
235 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
239 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
243 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
244 amdgpu_ring_write(ring, 0x8); in jpeg_v1_0_decode_ring_emit_fence()
247 …PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE… in jpeg_v1_0_decode_ring_emit_fence()
248 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_emit_fence()
251 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
252 amdgpu_ring_write(ring, 0x01400200); in jpeg_v1_0_decode_ring_emit_fence()
255 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
259 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
263 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
267 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2)); in jpeg_v1_0_decode_ring_emit_fence()
268 amdgpu_ring_write(ring, 0xffffffff); in jpeg_v1_0_decode_ring_emit_fence()
271 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
272 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v1_0_decode_ring_emit_fence()
275 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
276 amdgpu_ring_write(ring, 0x1); in jpeg_v1_0_decode_ring_emit_fence()
279 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v1_0_decode_ring_emit_fence()
280 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_emit_fence()
302 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
306 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
310 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
314 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
318 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
322 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
326 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
330 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v1_0_decode_ring_emit_ib()
331 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_emit_ib()
334 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
335 amdgpu_ring_write(ring, 0x01400200); in jpeg_v1_0_decode_ring_emit_ib()
338 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
339 amdgpu_ring_write(ring, 0x2); in jpeg_v1_0_decode_ring_emit_ib()
342 …PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_ib()
343 amdgpu_ring_write(ring, 0x2); in jpeg_v1_0_decode_ring_emit_ib()
354 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_reg_wait()
355 amdgpu_ring_write(ring, 0x01400200); in jpeg_v1_0_decode_ring_emit_reg_wait()
358 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_reg_wait()
362 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_reg_wait()
363 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_reg_wait()
364 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_reg_wait()
365 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_emit_reg_wait()
367 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_reg_wait()
371 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); in jpeg_v1_0_decode_ring_emit_reg_wait()
387 mask = 0xffffffff; in jpeg_v1_0_decode_ring_emit_vm_flush()
398 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_wreg()
399 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_wreg()
400 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_wreg()
401 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_emit_wreg()
403 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_wreg()
407 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_wreg()
418 for (i = 0; i < count / 2; i++) { in jpeg_v1_0_decode_ring_nop()
419 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v1_0_decode_ring_nop()
420 amdgpu_ring_write(ring, 0); in jpeg_v1_0_decode_ring_nop()
429 return 0; in jpeg_v1_0_set_interrupt_state()
444 entry->src_id, entry->src_data[0]); in jpeg_v1_0_process_interrupt()
448 return 0; in jpeg_v1_0_process_interrupt()
468 return 0; in jpeg_v1_0_early_init()
489 ring->vm_hub = AMDGPU_MMHUB0(0); in jpeg_v1_0_sw_init()
492 0, AMDGPU_RING_PRIO_DEFAULT, NULL); in jpeg_v1_0_sw_init()
496 adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] = in jpeg_v1_0_sw_init()
497 SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v1_0_sw_init()
499 return 0; in jpeg_v1_0_sw_init()
528 if (mode == 0) { in jpeg_v1_0_start()
529 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v1_0_start()
530 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | in jpeg_v1_0_start()
532 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); in jpeg_v1_0_start()
533 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); in jpeg_v1_0_start()
534 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v1_0_start()
535 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v1_0_start()
536 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); in jpeg_v1_0_start()
540 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_start()
549 .align_mask = 0xf,
550 .nop = PACKET0(0x81ff, 0),
601 int cnt = 0; in jpeg_v1_0_ring_begin_use()
608 for (cnt = 0; cnt < adev->vcn.num_enc_rings; cnt++) { in jpeg_v1_0_ring_begin_use()