amd/amdgpu/gmc_v10_0.c

229  * GART
236  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
251 	/* Use register 17 for GART */  in gmc_v10_0_flush_gpu_tlb()
695  * vram and gart within the GPU's physical address space.
724 	/* set the gart size */  in gmc_v10_0_mc_init()
750 	if (adev->gart.bo) {  in gmc_v10_0_gart_init()
751 		WARN(1, "NAVI10 PCIE GART already initialized\n");  in gmc_v10_0_gart_init()
755 	/* Initialize common gart structure */  in gmc_v10_0_gart_init()
760 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;  in gmc_v10_0_gart_init()
761 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |  in gmc_v10_0_gart_init()
911  * Tears down the driver GART/VM setup (CIK).
935  * gmc_v10_0_gart_enable - gart enable
944 	if (adev->gart.bo == NULL) {  in gmc_v10_0_gart_enable()
945 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");  in gmc_v10_0_gart_enable()
976 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",  in gmc_v10_0_gart_enable()
978 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));  in gmc_v10_0_gart_enable()
1017  * gmc_v10_0_gart_disable - gart disable