Lines Matching +full:0 +full:x00000100
63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
87 #define CLE_BPM_SERDES_CMD 0
91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
680 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
733 #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
734 #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT; in gfx_v8_0_init_golden_registers()
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) && in gfx_v8_0_init_golden_registers()
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || in gfx_v8_0_init_golden_registers()
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || in gfx_v8_0_init_golden_registers()
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) { in gfx_v8_0_init_golden_registers()
807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); in gfx_v8_0_init_golden_registers()
808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); in gfx_v8_0_init_golden_registers()
841 uint32_t tmp = 0; in gfx_v8_0_ring_test_ring()
845 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v8_0_ring_test_ring()
852 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
855 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_ring_test_ring()
857 if (tmp == 0xDEADBEEF) in gfx_v8_0_ring_test_ring()
884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); in gfx_v8_0_ring_test_ib()
885 memset(&ib, 0, sizeof(ib)); in gfx_v8_0_ring_test_ib()
891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
895 ib.ptr[4] = 0xDEADBEEF; in gfx_v8_0_ring_test_ib()
903 if (r == 0) { in gfx_v8_0_ring_test_ib()
906 } else if (r < 0) { in gfx_v8_0_ring_test_ib()
911 if (tmp == 0xDEADBEEF) in gfx_v8_0_ring_test_ib()
912 r = 0; in gfx_v8_0_ring_test_ib()
1085 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1092 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1133 err = 0; in gfx_v8_0_init_microcode()
1213 u32 count = 0, i; in gfx_v8_0_get_csb_buffer()
1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1226 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v8_0_get_csb_buffer()
1227 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v8_0_get_csb_buffer()
1236 for (i = 0; i < ext->reg_count; i++) in gfx_v8_0_get_csb_buffer()
1247 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1248 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1253 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1254 buffer[count++] = cpu_to_le32(0); in gfx_v8_0_get_csb_buffer()
1289 /* init spm vmid with 0xf */ in gfx_v8_0_rlc_init()
1291 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v8_0_rlc_init()
1293 return 0; in gfx_v8_0_rlc_init()
1307 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1325 memset(hpd, 0, mec_hpd_size); in gfx_v8_0_mec_init()
1331 return 0; in gfx_v8_0_mec_init()
1336 0x7e000209, 0x7e020208,
1337 0x7e040207, 0x7e060206,
1338 0x7e080205, 0x7e0a0204,
1339 0x7e0c0203, 0x7e0e0202,
1340 0x7e100201, 0x7e120200,
1341 0x7e140209, 0x7e160208,
1342 0x7e180207, 0x7e1a0206,
1343 0x7e1c0205, 0x7e1e0204,
1344 0x7e200203, 0x7e220202,
1345 0x7e240201, 0x7e260200,
1346 0x7e280209, 0x7e2a0208,
1347 0x7e2c0207, 0x7e2e0206,
1348 0x7e300205, 0x7e320204,
1349 0x7e340203, 0x7e360202,
1350 0x7e380201, 0x7e3a0200,
1351 0x7e3c0209, 0x7e3e0208,
1352 0x7e400207, 0x7e420206,
1353 0x7e440205, 0x7e460204,
1354 0x7e480203, 0x7e4a0202,
1355 0x7e4c0201, 0x7e4e0200,
1356 0x7e500209, 0x7e520208,
1357 0x7e540207, 0x7e560206,
1358 0x7e580205, 0x7e5a0204,
1359 0x7e5c0203, 0x7e5e0202,
1360 0x7e600201, 0x7e620200,
1361 0x7e640209, 0x7e660208,
1362 0x7e680207, 0x7e6a0206,
1363 0x7e6c0205, 0x7e6e0204,
1364 0x7e700203, 0x7e720202,
1365 0x7e740201, 0x7e760200,
1366 0x7e780209, 0x7e7a0208,
1367 0x7e7c0207, 0x7e7e0206,
1368 0xbf8a0000, 0xbf810000,
1373 0xbe8a0100, 0xbe8c0102,
1374 0xbe8e0104, 0xbe900106,
1375 0xbe920108, 0xbe940100,
1376 0xbe960102, 0xbe980104,
1377 0xbe9a0106, 0xbe9c0108,
1378 0xbe9e0100, 0xbea00102,
1379 0xbea20104, 0xbea40106,
1380 0xbea60108, 0xbea80100,
1381 0xbeaa0102, 0xbeac0104,
1382 0xbeae0106, 0xbeb00108,
1383 0xbeb20100, 0xbeb40102,
1384 0xbeb60104, 0xbeb80106,
1385 0xbeba0108, 0xbebc0100,
1386 0xbebe0102, 0xbec00104,
1387 0xbec20106, 0xbec40108,
1388 0xbec60100, 0xbec80102,
1389 0xbee60004, 0xbee70005,
1390 0xbeea0006, 0xbeeb0007,
1391 0xbee80008, 0xbee90009,
1392 0xbefc0000, 0xbf8a0000,
1393 0xbf810000, 0x00000000,
1398 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1399 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1403 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1405 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1406 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1407 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1408 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1409 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1410 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1411 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1412 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1413 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1414 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1419 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1420 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1424 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1426 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1427 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1428 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1429 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1430 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1431 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1432 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1433 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1434 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1435 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1440 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1441 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1445 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1447 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1448 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1449 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1450 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1451 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1452 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1453 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1454 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1455 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1456 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1490 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1500 return 0; in gfx_v8_0_do_edc_gpr_workarounds()
1504 return 0; in gfx_v8_0_do_edc_gpr_workarounds()
1507 WREG32(mmGB_EDC_MODE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1522 memset(&ib, 0, sizeof(ib)); in gfx_v8_0_do_edc_gpr_workarounds()
1531 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1534 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1537 /* init the ib length to 0 */ in gfx_v8_0_do_edc_gpr_workarounds()
1538 ib.length_dw = 0; in gfx_v8_0_do_edc_gpr_workarounds()
1542 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1560 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1563 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1568 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1586 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1589 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1594 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1612 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1615 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1637 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; in gfx_v8_0_do_edc_gpr_workarounds()
1642 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1672 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1673 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1674 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1675 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1689 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1690 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1691 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1692 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1704 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1705 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1706 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1707 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1719 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1720 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1721 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1722 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1736 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1737 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1738 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1753 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1754 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1755 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1756 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1771 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1772 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1773 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1789 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1790 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1816 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map… in gfx_v8_0_gpu_early_init()
1817 dimm00_addr_map = 0; in gfx_v8_0_gpu_early_init()
1818 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map… in gfx_v8_0_gpu_early_init()
1819 dimm01_addr_map = 0; in gfx_v8_0_gpu_early_init()
1820 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map… in gfx_v8_0_gpu_early_init()
1821 dimm10_addr_map = 0; in gfx_v8_0_gpu_early_init()
1822 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map… in gfx_v8_0_gpu_early_init()
1823 dimm11_addr_map = 0; in gfx_v8_0_gpu_early_init()
1846 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
1857 return 0; in gfx_v8_0_gpu_early_init()
1895 return 0; in gfx_v8_0_compute_ring_init()
1981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2000 ring_id = 0; in gfx_v8_0_sw_init()
2001 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2002 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2003 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2004 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v8_0_sw_init()
2019 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0); in gfx_v8_0_sw_init()
2025 kiq = &adev->gfx.kiq[0]; in gfx_v8_0_sw_init()
2026 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); in gfx_v8_0_sw_init()
2031 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0); in gfx_v8_0_sw_init()
2035 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2041 return 0; in gfx_v8_0_sw_init()
2049 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2051 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2054 amdgpu_gfx_mqd_sw_fini(adev, 0); in gfx_v8_0_sw_fini()
2055 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v8_0_sw_fini()
2056 amdgpu_gfx_kiq_fini(adev, 0); in gfx_v8_0_sw_fini()
2071 return 0; in gfx_v8_0_sw_fini()
2084 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2085 modearray[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2087 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2088 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2092 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2195 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2252 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2257 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2264 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2387 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2444 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2447 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2453 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2576 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2633 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2636 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2643 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2766 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2836 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2839 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2845 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2968 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3038 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3041 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3047 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3150 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3207 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3212 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3224 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3327 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3384 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3389 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3403 if (instance == 0xffffffff) in gfx_v8_0_select_se_sh()
3404 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3406 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3408 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3413 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3465 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3471 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3474 *rconf |= 0x0; in gfx_v8_0_raster_config()
3475 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3478 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v8_0_raster_config()
3495 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3496 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3504 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3508 if (!se_mask[0] && !se_mask[1]) { in gfx_v8_0_write_harvested_raster_configs()
3517 for (se = 0; se < num_se; se++) { in gfx_v8_0_write_harvested_raster_configs()
3583 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_write_harvested_raster_configs()
3589 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_write_harvested_raster_configs()
3596 u32 raster_config = 0, raster_config_1 = 0; in gfx_v8_0_setup_rb()
3597 u32 active_rbs = 0; in gfx_v8_0_setup_rb()
3603 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3604 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3605 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v8_0_setup_rb()
3611 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_setup_rb()
3632 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3633 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3634 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v8_0_setup_rb()
3645 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_setup_rb()
3649 #define DEFAULT_SH_MEM_BASES (0x6000)
3666 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v8_0_init_compute_vmid()
3667 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v8_0_init_compute_vmid()
3668 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v8_0_init_compute_vmid()
3681 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_init_compute_vmid()
3685 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v8_0_init_compute_vmid()
3688 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_init_compute_vmid()
3694 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); in gfx_v8_0_init_compute_vmid()
3695 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); in gfx_v8_0_init_compute_vmid()
3696 WREG32(amdgpu_gds_reg_offset[i].gws, 0); in gfx_v8_0_init_compute_vmid()
3697 WREG32(amdgpu_gds_reg_offset[i].oa, 0); in gfx_v8_0_init_compute_vmid()
3712 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); in gfx_v8_0_init_gds_vmid()
3713 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); in gfx_v8_0_init_gds_vmid()
3714 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); in gfx_v8_0_init_gds_vmid()
3715 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); in gfx_v8_0_init_gds_vmid()
3727 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3737 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_constants_init()
3749 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, in gfx_v8_0_constants_init()
3758 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { in gfx_v8_0_constants_init()
3759 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_constants_init()
3761 if (i == 0) { in gfx_v8_0_constants_init()
3762 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); in gfx_v8_0_constants_init()
3767 WREG32(mmSH_MEM_BASES, 0); in gfx_v8_0_constants_init()
3769 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); in gfx_v8_0_constants_init()
3779 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v8_0_constants_init()
3781 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_constants_init()
3792 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_constants_init()
3821 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3822 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3823 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v8_0_wait_for_rlc_serdes()
3824 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
3825 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v8_0_wait_for_rlc_serdes()
3830 gfx_v8_0_select_se_sh(adev, 0xffffffff, in gfx_v8_0_wait_for_rlc_serdes()
3831 0xffffffff, 0xffffffff, 0); in gfx_v8_0_wait_for_rlc_serdes()
3839 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_wait_for_rlc_serdes()
3846 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
3847 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v8_0_wait_for_rlc_serdes()
3858 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3859 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3860 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3873 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3900 if (register_list_format[ind_offset] == 0xFFFFFFFF) { in gfx_v8_0_parse_ind_reg_list()
3908 for (indices = 0; in gfx_v8_0_parse_ind_reg_list()
3931 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; in gfx_v8_0_init_save_restore_list()
3932 int indices_count = 0; in gfx_v8_0_init_save_restore_list()
3933 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; in gfx_v8_0_init_save_restore_list()
3934 int offset_count = 0; in gfx_v8_0_init_save_restore_list()
3956 WREG32(mmRLC_SRM_ARAM_ADDR, 0); in gfx_v8_0_init_save_restore_list()
3957 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3962 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3973 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) in gfx_v8_0_init_save_restore_list()
3980 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) { in gfx_v8_0_init_save_restore_list()
3981 if (unique_indices[i] != 0) { in gfx_v8_0_init_save_restore_list()
3982 WREG32(temp + i, unique_indices[i] & 0x3FFFF); in gfx_v8_0_init_save_restore_list()
3988 return 0; in gfx_v8_0_init_save_restore_list()
4000 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); in gfx_v8_0_init_power_gating()
4002 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4003 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4004 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4005 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4008 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); in gfx_v8_0_init_power_gating()
4009 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); in gfx_v8_0_init_power_gating()
4016 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4022 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4027 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
4053 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4064 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v8_0_rlc_reset()
4083 return 0; in gfx_v8_0_rlc_resume()
4091 return 0; in gfx_v8_0_rlc_resume()
4099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4113 u32 count = 0; in gfx_v8_0_get_csb_size()
4127 return 0; in gfx_v8_0_get_csb_size()
4142 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4149 WREG32(mmCP_ENDIAN_SWAP, 0); in gfx_v8_0_cp_gfx_start()
4161 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4165 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4166 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4176 for (i = 0; i < ext->reg_count; i++) in gfx_v8_0_cp_gfx_start()
4184 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4185 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4187 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4190 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
4191 amdgpu_ring_write(ring, 0); in gfx_v8_0_cp_gfx_start()
4196 amdgpu_ring_write(ring, 0x8000); in gfx_v8_0_cp_gfx_start()
4197 amdgpu_ring_write(ring, 0x8000); in gfx_v8_0_cp_gfx_start()
4201 return 0; in gfx_v8_0_cp_gfx_start()
4216 DOORBELL_HIT, 0); in gfx_v8_0_set_cpg_door_bell()
4220 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); in gfx_v8_0_set_cpg_door_bell()
4228 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, in gfx_v8_0_set_cpg_door_bell()
4245 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v8_0_cp_gfx_resume()
4247 /* set the RB to use vmid 0 */ in gfx_v8_0_cp_gfx_resume()
4248 WREG32(mmCP_RB_VMID, 0); in gfx_v8_0_cp_gfx_resume()
4251 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4253 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4264 ring->wptr = 0; in gfx_v8_0_cp_gfx_resume()
4270 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v8_0_cp_gfx_resume()
4287 return 0; in gfx_v8_0_cp_gfx_resume()
4293 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable()
4296 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4309 tmp &= 0xffffff00; in gfx_v8_0_kiq_setting()
4312 tmp |= 0x80; in gfx_v8_0_kiq_setting()
4318 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_kcq_enable()
4319 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable()
4322 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { in gfx_v8_0_kiq_kcq_enable()
4323 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4344 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx_v8_0_kiq_kcq_enable()
4347 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v8_0_kiq_kcq_enable()
4348 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v8_0_kiq_kcq_enable()
4349 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v8_0_kiq_kcq_enable()
4350 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v8_0_kiq_kcq_enable()
4351 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4358 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ in gfx_v8_0_kiq_kcq_enable()
4365 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */ in gfx_v8_0_kiq_kcq_enable()
4374 return 0; in gfx_v8_0_kiq_kcq_enable()
4379 int i, r = 0; in gfx_v8_0_deactivate_hqd()
4383 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_deactivate_hqd()
4391 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
4392 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v8_0_deactivate_hqd()
4393 WREG32(mmCP_HQD_PQ_WPTR, 0); in gfx_v8_0_deactivate_hqd()
4418 mqd->header = 0xC0310800; in gfx_v8_0_mqd_init()
4419 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v8_0_mqd_init()
4420 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v8_0_mqd_init()
4421 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v8_0_mqd_init()
4422 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v8_0_mqd_init()
4423 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v8_0_mqd_init()
4424 mqd->compute_misc_reserved = 0x00000003; in gfx_v8_0_mqd_init()
4444 ring->use_doorbell ? 1 : 0); in gfx_v8_0_mqd_init()
4449 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4452 /* set MQD vmid to 0 */ in gfx_v8_0_mqd_init()
4454 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v8_0_mqd_init()
4471 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4479 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4481 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4485 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4486 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4488 tmp = 0; in gfx_v8_0_mqd_init()
4498 DOORBELL_SOURCE, 0); in gfx_v8_0_mqd_init()
4500 DOORBELL_HIT, 0); in gfx_v8_0_mqd_init()
4506 ring->wptr = 0; in gfx_v8_0_mqd_init()
4511 mqd->cp_hqd_vmid = 0; in gfx_v8_0_mqd_init()
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); in gfx_v8_0_mqd_init()
4555 return 0; in gfx_v8_0_mqd_init()
4568 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v8_0_mqd_commit()
4592 return 0; in gfx_v8_0_mqd_commit()
4604 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4605 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4608 ring->wptr = 0; in gfx_v8_0_kiq_init_queue()
4611 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kiq_init_queue()
4613 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kiq_init_queue()
4616 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4617 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v8_0_kiq_init_queue()
4618 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v8_0_kiq_init_queue()
4622 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kiq_init_queue()
4625 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kiq_init_queue()
4628 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4629 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4632 return 0; in gfx_v8_0_kiq_init_queue()
4639 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4642 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4643 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v8_0_kcq_init_queue()
4644 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v8_0_kcq_init_queue()
4646 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kcq_init_queue()
4648 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kcq_init_queue()
4658 ring->wptr = 0; in gfx_v8_0_kcq_init_queue()
4661 return 0; in gfx_v8_0_kcq_init_queue()
4679 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_resume()
4682 if (unlikely(r != 0)) in gfx_v8_0_kiq_resume()
4686 if (unlikely(r != 0)) { in gfx_v8_0_kiq_resume()
4695 return 0; in gfx_v8_0_kiq_resume()
4701 int r = 0, i; in gfx_v8_0_kcq_resume()
4705 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4709 if (unlikely(r != 0)) in gfx_v8_0_kcq_resume()
4738 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4743 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_cp_test_all_rings()
4748 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4753 return 0; in gfx_v8_0_cp_test_all_rings()
4781 return 0; in gfx_v8_0_cp_resume()
4810 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kcq_disable()
4816 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4820 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v8_0_kcq_disable()
4822 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | in gfx_v8_0_kcq_disable()
4823 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | in gfx_v8_0_kcq_disable()
4826 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4827 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4828 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4842 || RREG32(mmGRBM_STATUS2) != 0x8) in gfx_v8_0_is_idle()
4852 if (RREG32(mmGRBM_STATUS2) != 0x8) in gfx_v8_0_rlc_is_idle()
4863 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_wait_for_rlc_idle()
4865 return 0; in gfx_v8_0_wait_for_rlc_idle()
4877 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_wait_for_idle()
4879 return 0; in gfx_v8_0_wait_for_idle()
4890 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4891 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4893 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4895 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4902 return 0; in gfx_v8_0_hw_fini()
4904 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v8_0_hw_fini()
4913 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v8_0_hw_fini()
4915 return 0; in gfx_v8_0_hw_fini()
4931 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
4984 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
4985 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
4993 u32 grbm_soft_reset = 0; in gfx_v8_0_pre_soft_reset()
4997 return 0; in gfx_v8_0_pre_soft_reset()
5015 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5019 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_pre_soft_reset()
5021 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_pre_soft_reset()
5028 return 0; in gfx_v8_0_pre_soft_reset()
5034 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v8_0_soft_reset()
5039 return 0; in gfx_v8_0_soft_reset()
5055 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
5069 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
5082 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); in gfx_v8_0_soft_reset()
5083 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); in gfx_v8_0_soft_reset()
5090 return 0; in gfx_v8_0_soft_reset()
5096 u32 grbm_soft_reset = 0; in gfx_v8_0_post_soft_reset()
5100 return 0; in gfx_v8_0_post_soft_reset()
5110 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5114 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_post_soft_reset()
5116 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_post_soft_reset()
5131 return 0; in gfx_v8_0_post_soft_reset()
5162 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5163 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5165 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5170 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5171 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5173 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5178 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5179 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5181 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5186 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5187 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5189 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5220 /* type 0 wave data */ in gfx_v8_0_read_wave_data()
5221 dst[(*no_fields)++] = 0; in gfx_v8_0_read_wave_data()
5248 adev, simd, wave, 0, in gfx_v8_0_read_wave_sgprs()
5275 return 0; in gfx_v8_0_early_init()
5283 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5287 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5296 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5302 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5310 return 0; in gfx_v8_0_late_init()
5322 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5328 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5334 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5340 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5346 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
5373 return 0; in gfx_v8_0_set_powergating_state()
5379 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v8_0_set_powergating_state()
5433 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v8_0_set_powergating_state()
5434 return 0; in gfx_v8_0_set_powergating_state()
5443 *flags = 0; in gfx_v8_0_get_clockgating_state()
5484 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_send_serdes_cmd()
5486 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
5487 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
5515 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); in gfx_v8_0_send_serdes_cmd()
5521 #define MSG_EXIT_RLC_SAFE_MODE 0
5522 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5523 #define RLC_GPR_REG2__REQ__SHIFT 0
5524 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5525 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5549 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_set_safe_mode()
5558 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_set_safe_mode()
5575 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_unset_safe_mode()
5624 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v8_0_update_medium_grain_clock_gating()
5662 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); in gfx_v8_0_update_medium_grain_clock_gating()
5669 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); in gfx_v8_0_update_medium_grain_clock_gating()
5678 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */ in gfx_v8_0_update_medium_grain_clock_gating()
5720 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v8_0_update_medium_grain_clock_gating()
5730 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v8_0_update_coarse_grain_clock_gating()
5813 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v8_0_update_coarse_grain_clock_gating()
5831 return 0; in gfx_v8_0_update_gfx_clock_gating()
5837 uint32_t msg_id, pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5838 uint32_t pp_support_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5850 pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5871 pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5880 return 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5887 uint32_t msg_id, pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5888 uint32_t pp_support_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5900 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5919 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5940 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5953 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5968 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5978 return 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5987 return 0; in gfx_v8_0_set_clockgating_state()
6008 return 0; in gfx_v8_0_set_clockgating_state()
6057 reg_mem_engine = 0; in gfx_v8_0_ring_emit_hdp_flush()
6071 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v8_0_ring_emit_hdp_flush()
6076 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6080 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6082 EVENT_INDEX(0)); in gfx_v8_0_ring_emit_vgt_flush()
6091 u32 header, control = 0; in gfx_v8_0_ring_emit_ib_gfx()
6110 (2 << 0) | in gfx_v8_0_ring_emit_ib_gfx()
6112 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v8_0_ring_emit_ib_gfx()
6113 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v8_0_ring_emit_ib_gfx()
6133 * GDS to 0 for this ring (me/pipe). in gfx_v8_0_ring_emit_ib_compute()
6144 (2 << 0) | in gfx_v8_0_ring_emit_ib_compute()
6146 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v8_0_ring_emit_ib_compute()
6147 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v8_0_ring_emit_ib_compute()
6166 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_gfx()
6167 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v8_0_ring_emit_fence_gfx()
6168 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()
6180 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_gfx()
6181 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v8_0_ring_emit_fence_gfx()
6182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6198 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_pipeline_sync()
6199 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v8_0_ring_emit_pipeline_sync()
6201 amdgpu_ring_write(ring, 0xffffffff); in gfx_v8_0_ring_emit_pipeline_sync()
6214 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in gfx_v8_0_ring_emit_vm_flush()
6215 WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v8_0_ring_emit_vm_flush()
6216 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v8_0_ring_emit_vm_flush()
6218 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_vm_flush()
6219 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v8_0_ring_emit_vm_flush()
6220 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v8_0_ring_emit_vm_flush()
6221 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v8_0_ring_emit_vm_flush()
6226 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v8_0_ring_emit_vm_flush()
6227 amdgpu_ring_write(ring, 0x0); in gfx_v8_0_ring_emit_vm_flush()
6259 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
6260 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_compute()
6274 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_fence_kiq()
6283 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_fence_kiq()
6284 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6286 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_fence_kiq()
6287 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ in gfx_v8_0_ring_emit_fence_kiq()
6293 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v8_ring_emit_sb()
6294 amdgpu_ring_write(ring, 0); in gfx_v8_ring_emit_sb()
6299 uint32_t dw2 = 0; in gfx_v8_ring_emit_cntxcntl()
6304 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v8_ring_emit_cntxcntl()
6308 dw2 |= 0x8001; in gfx_v8_ring_emit_cntxcntl()
6310 dw2 |= 0x01000000; in gfx_v8_ring_emit_cntxcntl()
6312 dw2 |= 0x10002; in gfx_v8_ring_emit_cntxcntl()
6316 dw2 |= 0x10000000; in gfx_v8_ring_emit_cntxcntl()
6322 dw2 |= 0x10000000; in gfx_v8_ring_emit_cntxcntl()
6327 amdgpu_ring_write(ring, 0); in gfx_v8_ring_emit_cntxcntl()
6337 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ in gfx_v8_0_ring_emit_init_cond_exec()
6339 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ in gfx_v8_0_ring_emit_init_cond_exec()
6348 BUG_ON(ring->ring[offset] != 0x55aa55aa); in gfx_v8_0_ring_emit_patch_cond_exec()
6363 amdgpu_ring_write(ring, 0 | /* src: register*/ in gfx_v8_0_ring_emit_rreg()
6367 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_rreg()
6394 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_wreg()
6401 uint32_t value = 0; in gfx_v8_0_ring_soft_recovery()
6403 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v8_0_ring_soft_recovery()
6404 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v8_0_ring_soft_recovery()
6414 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()
6431 case 0: in gfx_v8_0_set_compute_eop_interrupt_state()
6474 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()
6476 return 0; in gfx_v8_0_set_priv_reg_fault_state()
6485 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()
6487 return 0; in gfx_v8_0_set_priv_inst_fault_state()
6500 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v8_0_set_eop_interrupt_state()
6512 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v8_0_set_eop_interrupt_state()
6526 return 0; in gfx_v8_0_set_eop_interrupt_state()
6538 enable_flag = 0; in gfx_v8_0_set_cp_ecc_int_state()
6571 return 0; in gfx_v8_0_set_cp_ecc_int_state()
6587 enable_flag = 0; in gfx_v8_0_set_sq_int_state()
6597 return 0; in gfx_v8_0_set_sq_int_state()
6609 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v8_0_eop_irq()
6610 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v8_0_eop_irq()
6611 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v8_0_eop_irq()
6614 case 0: in gfx_v8_0_eop_irq()
6615 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6619 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6629 return 0; in gfx_v8_0_eop_irq()
6639 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v8_0_fault()
6640 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v8_0_fault()
6641 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v8_0_fault()
6644 case 0: in gfx_v8_0_fault()
6645 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6649 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6665 return 0; in gfx_v8_0_priv_reg_irq()
6674 return 0; in gfx_v8_0_priv_inst_irq()
6682 return 0; in gfx_v8_0_cp_ecc_error_irq()
6696 case 0: in gfx_v8_0_parse_sq_irq()
6726 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0); in gfx_v8_0_parse_sq_irq()
6730 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_parse_sq_irq()
6769 unsigned ih_data = entry->src_data[0]; in gfx_v8_0_sq_irq()
6783 return 0; in gfx_v8_0_sq_irq()
6794 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v8_0_emit_mem_sync()
6795 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v8_0_emit_mem_sync()
6796 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v8_0_emit_mem_sync()
6807 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v8_0_emit_mem_sync_compute()
6808 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ in gfx_v8_0_emit_mem_sync_compute()
6809 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v8_0_emit_mem_sync_compute()
6810 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v8_0_emit_mem_sync_compute()
6811 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v8_0_emit_mem_sync_compute()
6815 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6816 #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
6823 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT; in gfx_v8_0_emit_wave_limit_cs()
6826 case 0: in gfx_v8_0_emit_wave_limit_cs()
6847 #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
6858 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; in gfx_v8_0_emit_wave_limit()
6864 * amdgpu controls only 1st ME(0-3 CS pipes). in gfx_v8_0_emit_wave_limit()
6866 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v8_0_emit_wave_limit()
6897 .align_mask = 0xff,
6898 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6944 .align_mask = 0xff,
6945 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6978 .align_mask = 0xff,
6979 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7004 adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7006 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7009 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7098 int i, j, k, counter, active_cu_number = 0; in gfx_v8_0_get_cu_info()
7099 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v8_0_get_cu_info()
7104 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v8_0_get_cu_info()
7114 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7115 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7117 ao_bitmap = 0; in gfx_v8_0_get_cu_info()
7118 counter = 0; in gfx_v8_0_get_cu_info()
7119 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v8_0_get_cu_info()
7124 cu_info->bitmap[0][i][j] = bitmap; in gfx_v8_0_get_cu_info()
7126 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()
7140 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v8_0_get_cu_info()
7156 .minor = 0,
7157 .rev = 0,
7166 .rev = 0,
7193 WRITE_DATA_CACHE_POLICY(0)); in gfx_v8_0_ring_emit_ce_meta()
7226 WRITE_DATA_CACHE_POLICY(0)); in gfx_v8_0_ring_emit_de_meta()