56 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1	0x1388
59 #define regCGTT_WD_CLK_CTRL		0x5086
61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1	0x4e7e
63 #define regPC_CONFIG_CNTL_1		0x194d
94 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
99 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
100 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
101 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
102 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
103 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
104 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
105 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
106 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
107 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
145 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |  in gfx11_kiq_set_resources()
146 			  PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */  in gfx11_kiq_set_resources()
147 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */  in gfx11_kiq_set_resources()
150 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */  in gfx11_kiq_set_resources()
151 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */  in gfx11_kiq_set_resources()
152 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx11_kiq_set_resources()
153 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx11_kiq_set_resources()
161 	uint32_t me = 0, eng_sel = 0;  in gfx11_kiq_map_queues()
166 		eng_sel = 0;  in gfx11_kiq_map_queues()
169 		me = 0;  in gfx11_kiq_map_queues()
181 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/  in gfx11_kiq_map_queues()
182 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_map_queues()
183 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */  in gfx11_kiq_map_queues()
184 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */  in gfx11_kiq_map_queues()
188 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */  in gfx11_kiq_map_queues()
189 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */  in gfx11_kiq_map_queues()
205 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;  in gfx11_kiq_unmap_queues()
207 	if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {  in gfx11_kiq_unmap_queues()
213 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_unmap_queues()
215 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |  in gfx11_kiq_unmap_queues()
226 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
227 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
228 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
237 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;  in gfx11_kiq_query_status()
241 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |  in gfx11_kiq_query_status()
242 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |  in gfx11_kiq_query_status()
244 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_query_status()
275 	adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;  in gfx_v11_0_set_kiq_pm4_funcs()
283 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_init_golden_registers()
284 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_init_golden_registers()
285 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_init_golden_registers()
304 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));  in gfx_v11_0_write_data_to_reg()
306 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_write_data_to_reg()
317 			  /* memory (1) or register (0) */  in gfx_v11_0_wait_reg_mem()
324 		BUG_ON(addr0 & 0x3); /* Dword align */  in gfx_v11_0_wait_reg_mem()
335 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);  in gfx_v11_0_ring_test_ring()
336 	uint32_t tmp = 0;  in gfx_v11_0_ring_test_ring()
340 	WREG32(scratch, 0xCAFEDEAD);  in gfx_v11_0_ring_test_ring()
349 		gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);  in gfx_v11_0_ring_test_ring()
354 		amdgpu_ring_write(ring, 0xDEADBEEF);  in gfx_v11_0_ring_test_ring()
358 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_ring_test_ring()
360 		if (tmp == 0xDEADBEEF)  in gfx_v11_0_ring_test_ring()
386 		return 0;  in gfx_v11_0_ring_test_ib()
388 	memset(&ib, 0, sizeof(ib));  in gfx_v11_0_ring_test_ib()
402 		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);  in gfx_v11_0_ring_test_ib()
409 		adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);  in gfx_v11_0_ring_test_ib()
419 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v11_0_ring_test_ib()
423 	ib.ptr[4] = 0xDEADBEEF;  in gfx_v11_0_ring_test_ib()
431 	if (r == 0) {  in gfx_v11_0_ring_test_ib()
434 	} else if (r < 0) {  in gfx_v11_0_ring_test_ib()
438 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)  in gfx_v11_0_ring_test_ib()
439 		r = 0;  in gfx_v11_0_ring_test_ib()
465 	int err = 0;  in gfx_v11_0_init_toc_microcode()
479 	return 0;  in gfx_v11_0_init_toc_microcode()
487 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_check_fw_cp_gfx_shadow()
488 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_check_fw_cp_gfx_shadow()
489 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_check_fw_cp_gfx_shadow()
490 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_check_fw_cp_gfx_shadow()
526 				adev->gfx.pfp_fw->data, 2, 0);  in gfx_v11_0_init_microcode()
549 		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &&  in gfx_v11_0_init_microcode()
550 		    adev->pdev->revision == 0xCE)  in gfx_v11_0_init_microcode()
583 	/* only one MEC for gfx 11.0.0. */  in gfx_v11_0_init_microcode()
608 	u32 count = 0;  in gfx_v11_0_get_csb_size()
622 				return 0;  in gfx_v11_0_get_csb_size()
639 	u32 count = 0, i;  in gfx_v11_0_get_csb_buffer()
649 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_get_csb_buffer()
653 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v11_0_get_csb_buffer()
654 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v11_0_get_csb_buffer()
663 				for (i = 0; i < ext->reg_count; i++)  in gfx_v11_0_get_csb_buffer()
672 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;  in gfx_v11_0_get_csb_buffer()
677 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_get_csb_buffer()
680 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_get_csb_buffer()
681 	buffer[count++] = cpu_to_le32(0);  in gfx_v11_0_get_csb_buffer()
701 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];  in gfx_v11_0_init_rlcg_reg_access_ctrl()
702 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
703 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
704 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
705 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
706 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
707 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
708 	reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
728 	/* init spm vmid with 0xf */  in gfx_v11_0_rlc_init()
730 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);  in gfx_v11_0_rlc_init()
732 	return 0;  in gfx_v11_0_rlc_init()
755 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in gfx_v11_0_mec_init()
773 		memset(hpd, 0, mec_hpd_size);  in gfx_v11_0_mec_init()
779 	return 0;  in gfx_v11_0_mec_init()
784 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,  in wave_read_ind()
787 	return RREG32_SOC15(GC, 0, regSQ_IND_DATA);  in wave_read_ind()
794 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,  in wave_read_regs()
800 		*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);  in wave_read_regs()
808 	WARN_ON(simd != 0);  in gfx_v11_0_read_wave_data()
833 	WARN_ON(simd != 0);  in gfx_v11_0_read_wave_sgprs()
836 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,  in gfx_v11_0_read_wave_sgprs()
870 		return 0;  in gfx_v11_0_get_gfx_shadow_info()
872 		memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));  in gfx_v11_0_get_gfx_shadow_info()
890 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_gpu_early_init()
891 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_gpu_early_init()
892 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_gpu_early_init()
894 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
895 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
896 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;  in gfx_v11_0_gpu_early_init()
897 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;  in gfx_v11_0_gpu_early_init()
899 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_gpu_early_init()
902 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
903 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
904 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;  in gfx_v11_0_gpu_early_init()
905 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;  in gfx_v11_0_gpu_early_init()
907 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_gpu_early_init()
908 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_gpu_early_init()
909 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_gpu_early_init()
911 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
912 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
913 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;  in gfx_v11_0_gpu_early_init()
914 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;  in gfx_v11_0_gpu_early_init()
921 	return 0;  in gfx_v11_0_gpu_early_init()
944 	ring->vm_hub = AMDGPU_GFXHUB(0);  in gfx_v11_0_gfx_ring_init()
952 	return 0;  in gfx_v11_0_gfx_ring_init()
975 	ring->vm_hub = AMDGPU_GFXHUB(0);  in gfx_v11_0_compute_ring_init()
989 	return 0;  in gfx_v11_0_compute_ring_init()
1014 	uint32_t total_size = 0;  in gfx_v11_0_calc_toc_total_size()
1049 	return 0;  in gfx_v11_0_rlc_autoload_buffer_init()
1068 	if (fw_size == 0)  in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1077 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);  in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1090 	*(uint64_t *)fw_autoload_mask |= 0x1;  in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1092 	DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);  in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1239 		adev->sdma.instance[0].fw->data;  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1240 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1247 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1263 	for (pipe = 0; pipe < 2; pipe++) {  in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1264 		if (pipe==0) {  in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1297 	memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);  in gfx_v11_0_rlc_backdoor_autoload_enable()
1309 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));  in gfx_v11_0_rlc_backdoor_autoload_enable()
1310 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));  in gfx_v11_0_rlc_backdoor_autoload_enable()
1312 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);  in gfx_v11_0_rlc_backdoor_autoload_enable()
1326 	return 0;  in gfx_v11_0_rlc_backdoor_autoload_enable()
1331 	int i, j, k, r, ring_id = 0;  in gfx_v11_0_sw_init()
1335 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_sw_init()
1336 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_sw_init()
1337 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_sw_init()
1338 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_sw_init()
1346 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_sw_init()
1347 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_sw_init()
1348 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_sw_init()
1367 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&  in gfx_v11_0_sw_init()
1416 	for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_sw_init()
1417 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {  in gfx_v11_0_sw_init()
1418 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {  in gfx_v11_0_sw_init()
1431 	ring_id = 0;  in gfx_v11_0_sw_init()
1433 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v11_0_sw_init()
1434 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v11_0_sw_init()
1435 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v11_0_sw_init()
1436 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,  in gfx_v11_0_sw_init()
1451 		r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);  in gfx_v11_0_sw_init()
1457 		kiq = &adev->gfx.kiq[0];  in gfx_v11_0_sw_init()
1458 		r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);  in gfx_v11_0_sw_init()
1463 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);  in gfx_v11_0_sw_init()
1483 	return 0;  in gfx_v11_0_sw_init()
1520 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v11_0_sw_fini()
1522 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v11_0_sw_fini()
1525 	amdgpu_gfx_mqd_sw_fini(adev, 0);  in gfx_v11_0_sw_fini()
1528 		amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);  in gfx_v11_0_sw_fini()
1529 		amdgpu_gfx_kiq_fini(adev, 0);  in gfx_v11_0_sw_fini()
1542 	return 0;  in gfx_v11_0_sw_fini()
1550 	if (instance == 0xffffffff)  in gfx_v11_0_select_se_sh()
1551 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,  in gfx_v11_0_select_se_sh()
1554 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,  in gfx_v11_0_select_se_sh()
1557 	if (se_num == 0xffffffff)  in gfx_v11_0_select_se_sh()
1563 	if (sh_num == 0xffffffff)  in gfx_v11_0_select_se_sh()
1569 	WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);  in gfx_v11_0_select_se_sh()
1576 	gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);  in gfx_v11_0_get_sa_active_bitmap()
1580 	gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);  in gfx_v11_0_get_sa_active_bitmap()
1595 	gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);  in gfx_v11_0_get_rb_active_bitmap()
1599 	gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);  in gfx_v11_0_get_rb_active_bitmap()
1615 	u32 active_rb_bitmap = 0;  in gfx_v11_0_setup_rb()
1628 	for (i = 0; i < max_sa; i++) {  in gfx_v11_0_setup_rb()
1630 			active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));  in gfx_v11_0_setup_rb()
1638 #define DEFAULT_SH_MEM_BASES	(0x6000)
1639 #define LDS_APP_BASE           0x1
1640 #define SCRATCH_APP_BASE       0x2
1650 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)  in gfx_v11_0_init_compute_vmid()
1651 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)  in gfx_v11_0_init_compute_vmid()
1652 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)  in gfx_v11_0_init_compute_vmid()
1659 		soc21_grbm_select(adev, 0, 0, 0, i);  in gfx_v11_0_init_compute_vmid()
1661 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);  in gfx_v11_0_init_compute_vmid()
1662 		WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);  in gfx_v11_0_init_compute_vmid()
1665 		data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);  in gfx_v11_0_init_compute_vmid()
1667 		WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);  in gfx_v11_0_init_compute_vmid()
1669 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_init_compute_vmid()
1675 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);  in gfx_v11_0_init_compute_vmid()
1676 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);  in gfx_v11_0_init_compute_vmid()
1677 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);  in gfx_v11_0_init_compute_vmid()
1678 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);  in gfx_v11_0_init_compute_vmid()
1693 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);  in gfx_v11_0_init_gds_vmid()
1694 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);  in gfx_v11_0_init_gds_vmid()
1695 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);  in gfx_v11_0_init_gds_vmid()
1696 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);  in gfx_v11_0_init_gds_vmid()
1708 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |  in gfx_v11_0_get_tcc_info()
1709 			       RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);  in gfx_v11_0_get_tcc_info()
1722 		WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);  in gfx_v11_0_constants_init()
1727 	adev->gfx.config.pa_sc_tile_steering_override = 0;  in gfx_v11_0_constants_init()
1730 	tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);  in gfx_v11_0_constants_init()
1737 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {  in gfx_v11_0_constants_init()
1738 		soc21_grbm_select(adev, 0, 0, 0, i);  in gfx_v11_0_constants_init()
1740 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);  in gfx_v11_0_constants_init()
1741 		if (i != 0) {  in gfx_v11_0_constants_init()
1742 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,  in gfx_v11_0_constants_init()
1746 			WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);  in gfx_v11_0_constants_init()
1749 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_constants_init()
1765 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);  in gfx_v11_0_enable_gui_idle_interrupt()
1768 			    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
1770 			    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
1772 			    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
1774 			    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
1776 	WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);  in gfx_v11_0_enable_gui_idle_interrupt()
1783 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,  in gfx_v11_0_init_csb()
1785 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,  in gfx_v11_0_init_csb()
1786 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);  in gfx_v11_0_init_csb()
1787 	WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);  in gfx_v11_0_init_csb()
1789 	return 0;  in gfx_v11_0_init_csb()
1794 	u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);  in gfx_v11_0_rlc_stop()
1796 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);  in gfx_v11_0_rlc_stop()
1797 	WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);  in gfx_v11_0_rlc_stop()
1802 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);  in gfx_v11_0_rlc_reset()
1804 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);  in gfx_v11_0_rlc_reset()
1813 	rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);  in gfx_v11_0_rlc_smu_handshake_cntl()
1816 		/* RLC_PG_CNTL[23] = 0 (default)  in gfx_v11_0_rlc_smu_handshake_cntl()
1827 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);  in gfx_v11_0_rlc_smu_handshake_cntl()
1837 	WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);  in gfx_v11_0_rlc_start()
1846 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));  in gfx_v11_0_rlc_enable_srm()
1849 	WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);  in gfx_v11_0_rlc_enable_srm()
1863 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,  in gfx_v11_0_load_rlcg_microcode()
1866 	for (i = 0; i < fw_size; i++)  in gfx_v11_0_load_rlcg_microcode()
1867 		WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,  in gfx_v11_0_load_rlcg_microcode()
1870 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcg_microcode()
1886 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1888 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlc_iram_dram_microcode()
1891 		WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,  in gfx_v11_0_load_rlc_iram_dram_microcode()
1895 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1901 	WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1902 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlc_iram_dram_microcode()
1905 		WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,  in gfx_v11_0_load_rlc_iram_dram_microcode()
1909 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1911 	tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1913 	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1914 	WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);  in gfx_v11_0_load_rlc_iram_dram_microcode()
1930 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1932 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlcp_rlcv_microcode()
1935 		WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,  in gfx_v11_0_load_rlcp_rlcv_microcode()
1939 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1941 	tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1943 	WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1949 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1951 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlcp_rlcv_microcode()
1954 		WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,  in gfx_v11_0_load_rlcp_rlcv_microcode()
1958 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1960 	tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1962 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);  in gfx_v11_0_load_rlcp_rlcv_microcode()
1989 		return 0;  in gfx_v11_0_rlc_load_microcode()
2007 			return 0;  in gfx_v11_0_rlc_resume()
2013 		WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);  in gfx_v11_0_rlc_resume()
2016 		WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);  in gfx_v11_0_rlc_resume()
2029 	return 0;  in gfx_v11_0_rlc_resume()
2039 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache()
2041 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache()
2044 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache()
2045 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache()
2060 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_config_me_cache()
2061 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache()
2062 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache()
2063 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_me_cache()
2065 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache()
2068 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_config_me_cache()
2069 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_me_cache()
2070 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_config_me_cache()
2073 	return 0;  in gfx_v11_0_config_me_cache()
2083 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache()
2085 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache()
2088 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache()
2089 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache()
2104 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache()
2105 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache()
2106 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache()
2107 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_pfp_cache()
2109 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache()
2112 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_config_pfp_cache()
2113 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_pfp_cache()
2114 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_config_pfp_cache()
2117 	return 0;  in gfx_v11_0_config_pfp_cache()
2127 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache()
2130 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache()
2133 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache()
2134 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache()
2149 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_config_mec_cache()
2150 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache()
2151 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_mec_cache()
2153 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache()
2156 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,  in gfx_v11_0_config_mec_cache()
2157 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_mec_cache()
2158 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_config_mec_cache()
2161 	return 0;  in gfx_v11_0_config_mec_cache()
2174 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_config_pfp_cache_rs64()
2176 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2179 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2180 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2181 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2182 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2183 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2190 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2191 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2204 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2206 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2208 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2209 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2222 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_config_pfp_cache_rs64()
2223 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2224 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_config_pfp_cache_rs64()
2227 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2234 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2235 		if (pipe_id == 0)  in gfx_v11_0_config_pfp_cache_rs64()
2241 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2244 		if (pipe_id == 0)  in gfx_v11_0_config_pfp_cache_rs64()
2246 					PFP_PIPE0_RESET, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2249 					PFP_PIPE1_RESET, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2250 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2252 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,  in gfx_v11_0_config_pfp_cache_rs64()
2254 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2257 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2260 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2261 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2262 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2263 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2266 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2268 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2270 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2271 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2283 	return 0;  in gfx_v11_0_config_pfp_cache_rs64()
2296 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_config_me_cache_rs64()
2298 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_config_me_cache_rs64()
2301 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2302 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2303 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache_rs64()
2304 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_me_cache_rs64()
2305 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2312 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2313 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2326 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2328 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2331 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2332 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2345 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_config_me_cache_rs64()
2346 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_me_cache_rs64()
2347 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_config_me_cache_rs64()
2350 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_me_cache_rs64()
2357 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2358 		if (pipe_id == 0)  in gfx_v11_0_config_me_cache_rs64()
2364 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2367 		if (pipe_id == 0)  in gfx_v11_0_config_me_cache_rs64()
2369 					ME_PIPE0_RESET, 0);  in gfx_v11_0_config_me_cache_rs64()
2372 					ME_PIPE1_RESET, 0);  in gfx_v11_0_config_me_cache_rs64()
2373 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2375 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,  in gfx_v11_0_config_me_cache_rs64()
2377 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,  in gfx_v11_0_config_me_cache_rs64()
2380 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_me_cache_rs64()
2383 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2384 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2385 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache_rs64()
2386 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2389 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2391 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2393 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2394 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2406 	return 0;  in gfx_v11_0_config_me_cache_rs64()
2419 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2420 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2421 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_mec_cache_rs64()
2422 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache_rs64()
2423 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2425 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2426 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2427 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache_rs64()
2428 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2431 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2432 		soc21_grbm_select(adev, 1, i, 0, 0);  in gfx_v11_0_config_mec_cache_rs64()
2434 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);  in gfx_v11_0_config_mec_cache_rs64()
2435 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,  in gfx_v11_0_config_mec_cache_rs64()
2438 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_config_mec_cache_rs64()
2441 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_mec_cache_rs64()
2444 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);  in gfx_v11_0_config_mec_cache_rs64()
2445 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_config_mec_cache_rs64()
2449 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_mec_cache_rs64()
2452 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2454 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2457 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2458 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2471 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2473 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2476 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2477 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2489 	return 0;  in gfx_v11_0_config_mec_cache_rs64()
2507 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2508 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2509 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2512 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2515 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2518 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_gfx_rs64()
2521 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2524 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2525 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2526 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2529 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2530 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2531 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2534 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2537 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2540 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_gfx_rs64()
2543 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2546 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2547 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2548 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2551 	for (pipe_id = 0; pipe_id < 4; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2552 		soc21_grbm_select(adev, 1, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2553 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2556 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2559 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2562 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);  in gfx_v11_0_config_gfx_rs64()
2567 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2570 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2571 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2572 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2573 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2574 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2584 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_wait_for_rlc_autoload_complete()
2585 		cp_status = RREG32_SOC15(GC, 0, regCP_STAT);  in gfx_v11_0_wait_for_rlc_autoload_complete()
2587 		if (amdgpu_ip_version(adev, GC_HWIP, 0) ==  in gfx_v11_0_wait_for_rlc_autoload_complete()
2588 			    IP_VERSION(11, 0, 1) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2589 		    amdgpu_ip_version(adev, GC_HWIP, 0) ==  in gfx_v11_0_wait_for_rlc_autoload_complete()
2590 			    IP_VERSION(11, 0, 4) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2591 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0))  in gfx_v11_0_wait_for_rlc_autoload_complete()
2592 			bootload_status = RREG32_SOC15(GC, 0,  in gfx_v11_0_wait_for_rlc_autoload_complete()
2595 			bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);  in gfx_v11_0_wait_for_rlc_autoload_complete()
2597 		if ((cp_status == 0) &&  in gfx_v11_0_wait_for_rlc_autoload_complete()
2652 	return 0;  in gfx_v11_0_wait_for_rlc_autoload_complete()
2658 	u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_enable()
2660 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);  in gfx_v11_0_cp_gfx_enable()
2661 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);  in gfx_v11_0_cp_gfx_enable()
2662 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_enable()
2664 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_cp_gfx_enable()
2665 		if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)  in gfx_v11_0_cp_gfx_enable()
2673 	return 0;  in gfx_v11_0_cp_gfx_enable()
2710 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode()
2712 	for (i = 0; i < pfp_hdr->jt_size; i++)  in gfx_v11_0_cp_gfx_load_pfp_microcode()
2713 		WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,  in gfx_v11_0_cp_gfx_load_pfp_microcode()
2716 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);  in gfx_v11_0_cp_gfx_load_pfp_microcode()
2718 	return 0;  in gfx_v11_0_cp_gfx_load_pfp_microcode()
2782 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2784 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2787 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2788 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2789 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2790 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2791 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2798 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2799 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2812 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2814 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2816 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2817 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2830 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2831 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2832 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2835 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2842 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2843 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2849 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2852 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2854 					PFP_PIPE0_RESET, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2857 					PFP_PIPE1_RESET, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2858 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2860 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2862 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2865 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2868 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2869 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2870 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2871 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2874 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2876 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2878 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2879 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2891 	return 0;  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2928 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);  in gfx_v11_0_cp_gfx_load_me_microcode()
2930 	for (i = 0; i < me_hdr->jt_size; i++)  in gfx_v11_0_cp_gfx_load_me_microcode()
2931 		WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,  in gfx_v11_0_cp_gfx_load_me_microcode()
2934 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);  in gfx_v11_0_cp_gfx_load_me_microcode()
2936 	return 0;  in gfx_v11_0_cp_gfx_load_me_microcode()
3000 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3002 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3005 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3006 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3007 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3008 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3009 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3016 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3017 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3030 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3032 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3035 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3036 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3049 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3050 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3051 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3054 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3061 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3062 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3068 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3071 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3073 					ME_PIPE0_RESET, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3076 					ME_PIPE1_RESET, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3077 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3079 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3081 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3084 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3087 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3088 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3089 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3090 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3093 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3095 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3097 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3098 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3110 	return 0;  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3140 	return 0;  in gfx_v11_0_cp_gfx_load_microcode()
3152 	WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,  in gfx_v11_0_cp_gfx_start()
3154 	WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);  in gfx_v11_0_cp_gfx_start()
3159 	ring = &adev->gfx.gfx_ring[0];  in gfx_v11_0_cp_gfx_start()
3166 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_cp_gfx_start()
3170 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v11_0_cp_gfx_start()
3171 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v11_0_cp_gfx_start()
3181 				for (i = 0; i < ext->reg_count; i++)  in gfx_v11_0_cp_gfx_start()
3188 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;  in gfx_v11_0_cp_gfx_start()
3193 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_cp_gfx_start()
3196 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_cp_gfx_start()
3197 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_cp_gfx_start()
3201 	/* submit cs packet to copy state 0 to next available state */  in gfx_v11_0_cp_gfx_start()
3211 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_cp_gfx_start()
3212 		amdgpu_ring_write(ring, 0);  in gfx_v11_0_cp_gfx_start()
3216 	return 0;  in gfx_v11_0_cp_gfx_start()
3224 	tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_cp_gfx_switch_pipe()
3227 	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);  in gfx_v11_0_cp_gfx_switch_pipe()
3235 	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);  in gfx_v11_0_cp_gfx_set_doorbell()
3243 				    DOORBELL_EN, 0);  in gfx_v11_0_cp_gfx_set_doorbell()
3245 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);  in gfx_v11_0_cp_gfx_set_doorbell()
3247 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_gfx_set_doorbell()
3249 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);  in gfx_v11_0_cp_gfx_set_doorbell()
3251 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_gfx_set_doorbell()
3263 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);  in gfx_v11_0_cp_gfx_resume()
3265 	/* set the RB to use vmid 0 */  in gfx_v11_0_cp_gfx_resume()
3266 	WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);  in gfx_v11_0_cp_gfx_resume()
3268 	/* Init gfx ring 0 for pipe 0 */  in gfx_v11_0_cp_gfx_resume()
3273 	ring = &adev->gfx.gfx_ring[0];  in gfx_v11_0_cp_gfx_resume()
3275 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v11_0_cp_gfx_resume()
3277 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3280 	ring->wptr = 0;  in gfx_v11_0_cp_gfx_resume()
3281 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3282 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3286 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));  in gfx_v11_0_cp_gfx_resume()
3287 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &  in gfx_v11_0_cp_gfx_resume()
3291 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,  in gfx_v11_0_cp_gfx_resume()
3293 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,  in gfx_v11_0_cp_gfx_resume()
3297 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3300 	WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);  in gfx_v11_0_cp_gfx_resume()
3301 	WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));  in gfx_v11_0_cp_gfx_resume()
3303 	WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);  in gfx_v11_0_cp_gfx_resume()
3315 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v11_0_cp_gfx_resume()
3317 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3319 		ring->wptr = 0;  in gfx_v11_0_cp_gfx_resume()
3320 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3321 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3324 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));  in gfx_v11_0_cp_gfx_resume()
3325 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &  in gfx_v11_0_cp_gfx_resume()
3328 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,  in gfx_v11_0_cp_gfx_resume()
3330 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,  in gfx_v11_0_cp_gfx_resume()
3334 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3337 		WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);  in gfx_v11_0_cp_gfx_resume()
3338 		WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));  in gfx_v11_0_cp_gfx_resume()
3339 		WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);  in gfx_v11_0_cp_gfx_resume()
3344 	/* Switch to pipe 0 */  in gfx_v11_0_cp_gfx_resume()
3352 	return 0;  in gfx_v11_0_cp_gfx_resume()
3360 		data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);  in gfx_v11_0_cp_compute_enable()
3362 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3364 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3366 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3368 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3370 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3372 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3374 				                         enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3376 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3378 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3380 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3381 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);  in gfx_v11_0_cp_compute_enable()
3383 		data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);  in gfx_v11_0_cp_compute_enable()
3386 			data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);  in gfx_v11_0_cp_compute_enable()
3389 						     MEC_ME2_HALT, 0);  in gfx_v11_0_cp_compute_enable()
3394 		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);  in gfx_v11_0_cp_compute_enable()
3440 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);  in gfx_v11_0_cp_compute_load_microcode()
3442 	for (i = 0; i < mec_hdr->jt_size; i++)  in gfx_v11_0_cp_compute_load_microcode()
3443 		WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,  in gfx_v11_0_cp_compute_load_microcode()
3446 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);  in gfx_v11_0_cp_compute_load_microcode()
3448 	return 0;  in gfx_v11_0_cp_compute_load_microcode()
3510 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3511 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3512 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3513 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3514 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3516 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3517 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3518 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3519 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3522 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3523 		soc21_grbm_select(adev, 1, i, 0, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3525 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3526 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3529 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3532 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3535 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3536 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3540 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3543 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3545 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3548 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3549 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3562 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3564 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3567 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3568 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3580 	return 0;  in gfx_v11_0_cp_compute_load_microcode_rs64()
3589 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);  in gfx_v11_0_kiq_setting()
3590 	tmp &= 0xffffff00;  in gfx_v11_0_kiq_setting()
3592 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);  in gfx_v11_0_kiq_setting()
3593 	tmp |= 0x80;  in gfx_v11_0_kiq_setting()
3594 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);  in gfx_v11_0_kiq_setting()
3600 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_set_doorbell_range()
3602 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_set_doorbell_range()
3606 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_set_doorbell_range()
3608 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_set_doorbell_range()
3621 	mqd->cp_gfx_hqd_wptr = 0;  in gfx_v11_0_gfx_mqd_init()
3622 	mqd->cp_gfx_hqd_wptr_hi = 0;  in gfx_v11_0_gfx_mqd_init()
3625 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
3629 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);  in gfx_v11_0_gfx_mqd_init()
3630 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3632 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);  in gfx_v11_0_gfx_mqd_init()
3635 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */  in gfx_v11_0_gfx_mqd_init()
3636 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);  in gfx_v11_0_gfx_mqd_init()
3637 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3638 	mqd->cp_gfx_hqd_vmid = 0;  in gfx_v11_0_gfx_mqd_init()
3641 	 * 0x0 = low priority, 0x1 = high priority */  in gfx_v11_0_gfx_mqd_init()
3642 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);  in gfx_v11_0_gfx_mqd_init()
3643 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);  in gfx_v11_0_gfx_mqd_init()
3647 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);  in gfx_v11_0_gfx_mqd_init()
3658 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
3660 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_gfx_mqd_init()
3664 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
3665 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_gfx_mqd_init()
3669 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);  in gfx_v11_0_gfx_mqd_init()
3678 	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);  in gfx_v11_0_gfx_mqd_init()
3686 				    DOORBELL_EN, 0);  in gfx_v11_0_gfx_mqd_init()
3690 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);  in gfx_v11_0_gfx_mqd_init()
3695 	return 0;  in gfx_v11_0_gfx_mqd_init()
3702 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];  in gfx_v11_0_gfx_init_queue()
3705 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_gfx_init_queue()
3707 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_gfx_init_queue()
3709 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_gfx_init_queue()
3718 		ring->wptr = 0;  in gfx_v11_0_gfx_init_queue()
3719 		*ring->wptr_cpu_addr = 0;  in gfx_v11_0_gfx_init_queue()
3723 	return 0;  in gfx_v11_0_gfx_init_queue()
3731 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_cp_async_gfx_ring_resume()
3735 		if (unlikely(r != 0))  in gfx_v11_0_cp_async_gfx_ring_resume()
3749 	r = amdgpu_gfx_enable_kgq(adev, 0);  in gfx_v11_0_cp_async_gfx_ring_resume()
3763 	mqd->header = 0xC0310800;  in gfx_v11_0_compute_mqd_init()
3764 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v11_0_compute_mqd_init()
3765 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
3766 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
3767 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
3768 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
3769 	mqd->compute_misc_reserved = 0x00000007;  in gfx_v11_0_compute_mqd_init()
3776 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);  in gfx_v11_0_compute_mqd_init()
3783 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);  in gfx_v11_0_compute_mqd_init()
3791 				    DOORBELL_SOURCE, 0);  in gfx_v11_0_compute_mqd_init()
3793 				    DOORBELL_HIT, 0);  in gfx_v11_0_compute_mqd_init()
3796 				    DOORBELL_EN, 0);  in gfx_v11_0_compute_mqd_init()
3802 	mqd->cp_hqd_dequeue_request = 0;  in gfx_v11_0_compute_mqd_init()
3803 	mqd->cp_hqd_pq_rptr = 0;  in gfx_v11_0_compute_mqd_init()
3804 	mqd->cp_hqd_pq_wptr_lo = 0;  in gfx_v11_0_compute_mqd_init()
3805 	mqd->cp_hqd_pq_wptr_hi = 0;  in gfx_v11_0_compute_mqd_init()
3808 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
3811 	/* set MQD vmid to 0 */  in gfx_v11_0_compute_mqd_init()
3812 	tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);  in gfx_v11_0_compute_mqd_init()
3813 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v11_0_compute_mqd_init()
3822 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);  in gfx_v11_0_compute_mqd_init()
3836 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
3838 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_compute_mqd_init()
3842 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
3843 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_compute_mqd_init()
3845 	tmp = 0;  in gfx_v11_0_compute_mqd_init()
3848 		tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);  in gfx_v11_0_compute_mqd_init()
3855 				    DOORBELL_SOURCE, 0);  in gfx_v11_0_compute_mqd_init()
3857 				    DOORBELL_HIT, 0);  in gfx_v11_0_compute_mqd_init()
3863 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);  in gfx_v11_0_compute_mqd_init()
3866 	mqd->cp_hqd_vmid = 0;  in gfx_v11_0_compute_mqd_init()
3868 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);  in gfx_v11_0_compute_mqd_init()
3869 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);  in gfx_v11_0_compute_mqd_init()
3873 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);  in gfx_v11_0_compute_mqd_init()
3883 	return 0;  in gfx_v11_0_compute_mqd_init()
3894 		WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);  in gfx_v11_0_kiq_init_register()
3897 	WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);  in gfx_v11_0_kiq_init_register()
3900 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,  in gfx_v11_0_kiq_init_register()
3902 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,  in gfx_v11_0_kiq_init_register()
3906 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,  in gfx_v11_0_kiq_init_register()
3910 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,  in gfx_v11_0_kiq_init_register()
3914 	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {  in gfx_v11_0_kiq_init_register()
3915 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);  in gfx_v11_0_kiq_init_register()
3916 		for (j = 0; j < adev->usec_timeout; j++) {  in gfx_v11_0_kiq_init_register()
3917 			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))  in gfx_v11_0_kiq_init_register()
3921 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,  in gfx_v11_0_kiq_init_register()
3923 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,  in gfx_v11_0_kiq_init_register()
3925 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,  in gfx_v11_0_kiq_init_register()
3927 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,  in gfx_v11_0_kiq_init_register()
3932 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,  in gfx_v11_0_kiq_init_register()
3934 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,  in gfx_v11_0_kiq_init_register()
3937 	/* set MQD vmid to 0 */  in gfx_v11_0_kiq_init_register()
3938 	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,  in gfx_v11_0_kiq_init_register()
3942 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,  in gfx_v11_0_kiq_init_register()
3944 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,  in gfx_v11_0_kiq_init_register()
3948 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,  in gfx_v11_0_kiq_init_register()
3952 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,  in gfx_v11_0_kiq_init_register()
3954 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,  in gfx_v11_0_kiq_init_register()
3958 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,  in gfx_v11_0_kiq_init_register()
3960 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,  in gfx_v11_0_kiq_init_register()
3965 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,  in gfx_v11_0_kiq_init_register()
3967 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,  in gfx_v11_0_kiq_init_register()
3971 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,  in gfx_v11_0_kiq_init_register()
3975 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,  in gfx_v11_0_kiq_init_register()
3977 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,  in gfx_v11_0_kiq_init_register()
3981 	WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);  in gfx_v11_0_kiq_init_register()
3983 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,  in gfx_v11_0_kiq_init_register()
3987 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,  in gfx_v11_0_kiq_init_register()
3991 		WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);  in gfx_v11_0_kiq_init_register()
3993 	return 0;  in gfx_v11_0_kiq_init_register()
4005 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v11_0_kiq_init_queue()
4006 			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4009 		ring->wptr = 0;  in gfx_v11_0_kiq_init_queue()
4013 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kiq_init_queue()
4015 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kiq_init_queue()
4018 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4022 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kiq_init_queue()
4025 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kiq_init_queue()
4028 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v11_0_kiq_init_queue()
4029 			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4032 	return 0;  in gfx_v11_0_kiq_init_queue()
4039 	int mqd_idx = ring - &adev->gfx.compute_ring[0];  in gfx_v11_0_kcq_init_queue()
4042 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_kcq_init_queue()
4044 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kcq_init_queue()
4046 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kcq_init_queue()
4056 		ring->wptr = 0;  in gfx_v11_0_kcq_init_queue()
4057 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);  in gfx_v11_0_kcq_init_queue()
4061 	return 0;  in gfx_v11_0_kcq_init_queue()
4069 	ring = &adev->gfx.kiq[0].ring;  in gfx_v11_0_kiq_resume()
4072 	if (unlikely(r != 0))  in gfx_v11_0_kiq_resume()
4076 	if (unlikely(r != 0)) {  in gfx_v11_0_kiq_resume()
4086 	return 0;  in gfx_v11_0_kiq_resume()
4092 	int r = 0, i;  in gfx_v11_0_kcq_resume()
4097 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_kcq_resume()
4101 		if (unlikely(r != 0))  in gfx_v11_0_kcq_resume()
4114 	r = amdgpu_gfx_enable_kcq(adev, 0);  in gfx_v11_0_kcq_resume()
4169 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_cp_resume()
4176 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_cp_resume()
4183 	return 0;  in gfx_v11_0_cp_resume()
4207 	amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);  in gfx_v11_0_gfxhub_enable()
4209 	return 0;  in gfx_v11_0_gfxhub_enable()
4218 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);  in gfx_v11_0_select_cp_fw_arch()
4220 		WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);  in gfx_v11_0_select_cp_fw_arch()
4222 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);  in gfx_v11_0_select_cp_fw_arch()
4224 		WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);  in gfx_v11_0_select_cp_fw_arch()
4235 	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);  in get_gb_addr_config()
4236 	if (gb_addr_config == 0)  in get_gb_addr_config()
4264 	return 0;  in get_gb_addr_config()
4271 	data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);  in gfx_v11_0_disable_gpa_mode()
4273 	WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);  in gfx_v11_0_disable_gpa_mode()
4275 	data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);  in gfx_v11_0_disable_gpa_mode()
4277 	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);  in gfx_v11_0_disable_gpa_mode()
4297 			if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {  in gfx_v11_0_hw_init()
4374 		adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);  in gfx_v11_0_hw_init()
4383 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v11_0_hw_fini()
4384 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v11_0_hw_fini()
4388 			if (amdgpu_gfx_disable_kgq(adev, 0))  in gfx_v11_0_hw_fini()
4392 		if (amdgpu_gfx_disable_kcq(adev, 0))  in gfx_v11_0_hw_fini()
4404 		return 0;  in gfx_v11_0_hw_fini()
4413 	return 0;  in gfx_v11_0_hw_fini()
4430 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),  in gfx_v11_0_is_idle()
4443 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_wait_for_idle()
4445 		tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &  in gfx_v11_0_wait_for_idle()
4449 			return 0;  in gfx_v11_0_wait_for_idle()
4460 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_request_gfx_index_mutex()
4461 		/* Request with MeId=2, PipeId=0 */  in gfx_v11_0_request_gfx_index_mutex()
4462 		tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);  in gfx_v11_0_request_gfx_index_mutex()
4464 		WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);  in gfx_v11_0_request_gfx_index_mutex()
4466 		val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);  in gfx_v11_0_request_gfx_index_mutex()
4484 	return 0;  in gfx_v11_0_request_gfx_index_mutex()
4489 	u32 grbm_soft_reset = 0;  in gfx_v11_0_soft_reset()
4494 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_soft_reset()
4495 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4496 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4497 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4498 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4499 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);  in gfx_v11_0_soft_reset()
4501 	gfx_v11_0_set_safe_mode(adev, 0);  in gfx_v11_0_soft_reset()
4503 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v11_0_soft_reset()
4504 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v11_0_soft_reset()
4505 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v11_0_soft_reset()
4506 				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_soft_reset()
4510 				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);  in gfx_v11_0_soft_reset()
4512 				WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);  in gfx_v11_0_soft_reset()
4513 				WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);  in gfx_v11_0_soft_reset()
4517 	for (i = 0; i < adev->gfx.me.num_me; ++i) {  in gfx_v11_0_soft_reset()
4518 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {  in gfx_v11_0_soft_reset()
4519 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {  in gfx_v11_0_soft_reset()
4520 				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_soft_reset()
4524 				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);  in gfx_v11_0_soft_reset()
4526 				WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);  in gfx_v11_0_soft_reset()
4538 	WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);  in gfx_v11_0_soft_reset()
4541 	// to get sufficient time for GFX_HQD_ACTIVE reach 0  in gfx_v11_0_soft_reset()
4542 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4543 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4544 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4547 	r = gfx_v11_0_request_gfx_index_mutex(adev, 0);  in gfx_v11_0_soft_reset()
4553 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_soft_reset()
4554 		if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&  in gfx_v11_0_soft_reset()
4555 		    !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))  in gfx_v11_0_soft_reset()
4565 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in gfx_v11_0_soft_reset()
4576 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);  in gfx_v11_0_soft_reset()
4578 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in gfx_v11_0_soft_reset()
4580 					SOFT_RESET_CP, 0);  in gfx_v11_0_soft_reset()
4582 					SOFT_RESET_GFX, 0);  in gfx_v11_0_soft_reset()
4584 					SOFT_RESET_CPF, 0);  in gfx_v11_0_soft_reset()
4586 					SOFT_RESET_CPC, 0);  in gfx_v11_0_soft_reset()
4588 					SOFT_RESET_CPG, 0);  in gfx_v11_0_soft_reset()
4589 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);  in gfx_v11_0_soft_reset()
4591 	tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);  in gfx_v11_0_soft_reset()
4592 	tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);  in gfx_v11_0_soft_reset()
4593 	WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);  in gfx_v11_0_soft_reset()
4595 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);  in gfx_v11_0_soft_reset()
4596 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);  in gfx_v11_0_soft_reset()
4598 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_soft_reset()
4599 		if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))  in gfx_v11_0_soft_reset()
4604 		printk("Failed to wait CP_VMID_RESET to 0\n");  in gfx_v11_0_soft_reset()
4608 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_soft_reset()
4613 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);  in gfx_v11_0_soft_reset()
4615 	gfx_v11_0_unset_safe_mode(adev, 0);  in gfx_v11_0_soft_reset()
4627 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_check_soft_reset()
4634 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_check_soft_reset()
4660 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);  in gfx_v11_0_get_gpu_clock_counter()
4661 		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);  in gfx_v11_0_get_gpu_clock_counter()
4662 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);  in gfx_v11_0_get_gpu_clock_counter()
4664 			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);  in gfx_v11_0_get_gpu_clock_counter()
4669 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);  in gfx_v11_0_get_gpu_clock_counter()
4670 		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);  in gfx_v11_0_get_gpu_clock_counter()
4671 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);  in gfx_v11_0_get_gpu_clock_counter()
4673 			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);  in gfx_v11_0_get_gpu_clock_counter()
4690 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
4691 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,  in gfx_v11_0_ring_emit_gds_switch()
4695 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
4696 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,  in gfx_v11_0_ring_emit_gds_switch()
4700 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
4701 				    SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,  in gfx_v11_0_ring_emit_gds_switch()
4705 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
4706 				    SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,  in gfx_v11_0_ring_emit_gds_switch()
4738 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v11_0_late_init()
4742 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v11_0_late_init()
4746 	return 0;  in gfx_v11_0_late_init()
4754 	rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);  in gfx_v11_0_is_rlc_enabled()
4766 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);  in gfx_v11_0_set_safe_mode()
4769 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_set_safe_mode()
4770 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),  in gfx_v11_0_set_safe_mode()
4779 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);  in gfx_v11_0_unset_safe_mode()
4790 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_perf_clk()
4798 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_perf_clk()
4809 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_sram_fgcg()
4817 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_sram_fgcg()
4828 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_repeater_fgcg()
4836 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_repeater_fgcg()
4851 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_medium_grain_clock_gating()
4858 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_medium_grain_clock_gating()
4862 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_medium_grain_clock_gating()
4869 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_medium_grain_clock_gating()
4887 		def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_coarse_grain_clock_gating()
4900 			WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4902 		/* enable cgcg FSM(0x0000363F) */  in gfx_v11_0_update_coarse_grain_clock_gating()
4903 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4907 			data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
4913 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
4918 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4921 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_update_coarse_grain_clock_gating()
4925 			data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
4931 			data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
4936 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4938 		/* set IDLE_POLL_COUNT(0x00900100) */  in gfx_v11_0_update_coarse_grain_clock_gating()
4939 		def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4942 		data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
4943 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);  in gfx_v11_0_update_coarse_grain_clock_gating()
4946 			WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4948 		data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4953 		WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4955 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4957 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4961 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4963 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4967 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4976 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4979 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_update_coarse_grain_clock_gating()
4987 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4989 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4991 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
4995 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
4997 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5005 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_0_update_gfx_clock_gating()
5025 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_0_update_gfx_clock_gating()
5027 	return 0;  in gfx_v11_0_update_gfx_clock_gating()
5036 	data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);  in gfx_v11_0_update_spm_vmid()
5041 	WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);  in gfx_v11_0_update_spm_vmid()
5062 	u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);  in gfx_v11_cntl_power_gating()
5069 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);  in gfx_v11_cntl_power_gating()
5073 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_cntl_power_gating()
5074 		case IP_VERSION(11, 0, 1):  in gfx_v11_cntl_power_gating()
5075 		case IP_VERSION(11, 0, 4):  in gfx_v11_cntl_power_gating()
5076 		case IP_VERSION(11, 5, 0):  in gfx_v11_cntl_power_gating()
5077 			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);  in gfx_v11_cntl_power_gating()
5087 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_cntl_pg()
5091 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_cntl_pg()
5101 		return 0;  in gfx_v11_0_set_powergating_state()
5103 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_set_powergating_state()
5104 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_set_powergating_state()
5105 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_set_powergating_state()
5106 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_set_powergating_state()
5109 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_set_powergating_state()
5110 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_set_powergating_state()
5111 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_set_powergating_state()
5125 	return 0;  in gfx_v11_0_set_powergating_state()
5134 	        return 0;  in gfx_v11_0_set_clockgating_state()
5136 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_set_clockgating_state()
5137 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_set_clockgating_state()
5138 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_set_clockgating_state()
5139 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_set_clockgating_state()
5140 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_set_clockgating_state()
5141 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_set_clockgating_state()
5142 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_set_clockgating_state()
5150 	return 0;  in gfx_v11_0_set_clockgating_state()
5159 	data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_get_clockgating_state()
5176 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_get_clockgating_state()
5185 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_get_clockgating_state()
5209 		wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);  in gfx_v11_0_ring_get_wptr_gfx()
5210 		wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;  in gfx_v11_0_ring_get_wptr_gfx()
5226 		WREG32_SOC15(GC, 0, regCP_RB0_WPTR,  in gfx_v11_0_ring_set_wptr_gfx()
5228 		WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,  in gfx_v11_0_ring_set_wptr_gfx()
5282 		reg_mem_engine = 0;  in gfx_v11_0_ring_emit_hdp_flush()
5288 	gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,  in gfx_v11_0_ring_emit_hdp_flush()
5291 			       ref_and_mask, ref_and_mask, 0x20);  in gfx_v11_0_ring_emit_hdp_flush()
5300 	u32 header, control = 0;  in gfx_v11_0_ring_emit_ib_gfx()
5321 		control |= 0x400000;  in gfx_v11_0_ring_emit_ib_gfx()
5324 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */  in gfx_v11_0_ring_emit_ib_gfx()
5327 		(2 << 0) |  in gfx_v11_0_ring_emit_ib_gfx()
5344 		control |= 0x40000000;  in gfx_v11_0_ring_emit_ib_compute()
5354 	 * GDS to 0 for this ring (me/pipe).  in gfx_v11_0_ring_emit_ib_compute()
5363 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */  in gfx_v11_0_ring_emit_ib_compute()
5366 				(2 << 0) |  in gfx_v11_0_ring_emit_ib_compute()
5393 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));  in gfx_v11_0_ring_emit_fence()
5400 		BUG_ON(addr & 0x7);  in gfx_v11_0_ring_emit_fence()
5402 		BUG_ON(addr & 0x3);  in gfx_v11_0_ring_emit_fence()
5408 			 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);  in gfx_v11_0_ring_emit_fence()
5417 	gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),  in gfx_v11_0_ring_emit_pipeline_sync()
5418 			       upper_32_bits(addr), seq, 0xffffffff, 4);  in gfx_v11_0_ring_emit_pipeline_sync()
5425 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));  in gfx_v11_0_ring_invalidate_tlbs()
5437 		gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);  in gfx_v11_0_ring_emit_vm_flush()
5444 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v11_0_ring_emit_vm_flush()
5445 		amdgpu_ring_write(ring, 0x0);  in gfx_v11_0_ring_emit_vm_flush()
5459 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v11_0_ring_emit_fence_kiq()
5468 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v11_0_ring_emit_fence_kiq()
5469 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));  in gfx_v11_0_ring_emit_fence_kiq()
5470 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));  in gfx_v11_0_ring_emit_fence_kiq()
5471 		amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_fence_kiq()
5472 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */  in gfx_v11_0_ring_emit_fence_kiq()
5479 	uint32_t dw2 = 0;  in gfx_v11_0_ring_emit_cntxcntl()
5481 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */  in gfx_v11_0_ring_emit_cntxcntl()
5484 		dw2 |= 0x8001;  in gfx_v11_0_ring_emit_cntxcntl()
5486 		dw2 |= 0x01000000;  in gfx_v11_0_ring_emit_cntxcntl()
5488 		dw2 |= 0x10002;  in gfx_v11_0_ring_emit_cntxcntl()
5493 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_cntxcntl()
5514 			  PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5516 			  PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5526 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */  in gfx_v11_0_ring_emit_init_cond_exec()
5528 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */  in gfx_v11_0_ring_emit_init_cond_exec()
5537 	BUG_ON(ring->ring[offset] != 0x55aa55aa);  in gfx_v11_0_ring_emit_patch_cond_exec()
5548 	int i, r = 0;  in gfx_v11_0_ring_preempt_ib()
5550 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in gfx_v11_0_ring_preempt_ib()
5576 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_ring_preempt_ib()
5596 	struct v10_de_ib_state de_payload = {0};  in gfx_v11_0_ring_emit_de_meta()
5603 				  gfx[0].gfx_meta_data) +  in gfx_v11_0_ring_emit_de_meta()
5611 				  gfx[0].gds_backup) +  in gfx_v11_0_ring_emit_de_meta()
5632 				 WRITE_DATA_CACHE_POLICY(0));  in gfx_v11_0_ring_emit_de_meta()
5647 	uint32_t v = secure ? FRAME_TMZ : 0;  in gfx_v11_0_ring_emit_frame_cntl()
5649 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));  in gfx_v11_0_ring_emit_frame_cntl()
5650 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));  in gfx_v11_0_ring_emit_frame_cntl()
5659 	amdgpu_ring_write(ring, 0 |	/* src: register*/  in gfx_v11_0_ring_emit_rreg()
5663 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_rreg()
5673 	uint32_t cmd = 0;  in gfx_v11_0_ring_emit_wreg()
5689 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_wreg()
5696 	gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);  in gfx_v11_0_ring_emit_reg_wait()
5705 	gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,  in gfx_v11_0_ring_emit_reg_write_reg_wait()
5706 			       ref, mask, 0x20);  in gfx_v11_0_ring_emit_reg_write_reg_wait()
5713 	uint32_t value = 0;  in gfx_v11_0_ring_soft_recovery()
5715 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);  in gfx_v11_0_ring_soft_recovery()
5716 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);  in gfx_v11_0_ring_soft_recovery()
5719 	WREG32_SOC15(GC, 0, regSQ_CMD, value);  in gfx_v11_0_ring_soft_recovery()
5731 		case 0:  in gfx_v11_0_set_gfx_eop_interrupt_state()
5732 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
5735 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);  in gfx_v11_0_set_gfx_eop_interrupt_state()
5750 					    TIME_STAMP_INT_ENABLE, 0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
5752 					    GENERIC0_INT_ENABLE, 0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
5782 		case 0:  in gfx_v11_0_set_compute_eop_interrupt_state()
5783 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
5786 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
5789 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
5792 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
5807 					     TIME_STAMP_INT_ENABLE, 0);  in gfx_v11_0_set_compute_eop_interrupt_state()
5809 					     GENERIC0_INT_ENABLE, 0);  in gfx_v11_0_set_compute_eop_interrupt_state()
5832 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);  in gfx_v11_0_set_eop_interrupt_state()
5835 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);  in gfx_v11_0_set_eop_interrupt_state()
5838 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);  in gfx_v11_0_set_eop_interrupt_state()
5852 	return 0;  in gfx_v11_0_set_eop_interrupt_state()
5862 	uint32_t mes_queue_id = entry->src_data[0];  in gfx_v11_0_eop_irq()
5879 		me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v11_0_eop_irq()
5880 		pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v11_0_eop_irq()
5881 		queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v11_0_eop_irq()
5884 		case 0:  in gfx_v11_0_eop_irq()
5885 			if (pipe_id == 0)  in gfx_v11_0_eop_irq()
5886 				amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v11_0_eop_irq()
5892 			for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_eop_irq()
5907 	return 0;  in gfx_v11_0_eop_irq()
5918 		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,  in gfx_v11_0_set_priv_reg_fault_state()
5920 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_priv_reg_fault_state()
5926 	return 0;  in gfx_v11_0_set_priv_reg_fault_state()
5937 		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,  in gfx_v11_0_set_priv_inst_fault_state()
5939 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_priv_inst_fault_state()
5945 	return 0;  in gfx_v11_0_set_priv_inst_fault_state()
5955 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v11_0_handle_priv_fault()
5956 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v11_0_handle_priv_fault()
5957 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v11_0_handle_priv_fault()
5960 	case 0:  in gfx_v11_0_handle_priv_fault()
5961 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_handle_priv_fault()
5970 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_handle_priv_fault()
5989 	return 0;  in gfx_v11_0_priv_reg_irq()
5998 	return 0;  in gfx_v11_0_priv_inst_irq()
6008 	return 0;  in gfx_v11_0_rlc_gc_fed_irq()
6011 #if 0
6018 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6020 	target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6026 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6028 					    GENERIC2_INT_ENABLE, 0);
6029 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6033 					    GENERIC2_INT_ENABLE, 0);
6036 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6039 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6051 	return 0;
6069 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */  in gfx_v11_0_emit_mem_sync()
6070 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */  in gfx_v11_0_emit_mem_sync()
6071 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */  in gfx_v11_0_emit_mem_sync()
6072 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */  in gfx_v11_0_emit_mem_sync()
6073 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */  in gfx_v11_0_emit_mem_sync()
6074 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */  in gfx_v11_0_emit_mem_sync()
6100 	.align_mask = 0xff,
6101 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6150 	.align_mask = 0xff,
6151 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6185 	.align_mask = 0xff,
6186 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6217 	adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;  in gfx_v11_0_set_ring_funcs()
6219 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v11_0_set_ring_funcs()
6222 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v11_0_set_ring_funcs()
6256 	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */  in gfx_v11_0_set_irq_funcs()
6282 	adev->gds.gds_size = 0x1000;  in gfx_v11_0_set_gds_init()
6313 	WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);  in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
6319 	data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);  in gfx_v11_0_get_wgp_active_bitmap_per_sh()
6320 	data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);  in gfx_v11_0_get_wgp_active_bitmap_per_sh()
6337 	cu_active_bitmap = 0;  in gfx_v11_0_get_cu_active_bitmap_per_sh()
6339 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {  in gfx_v11_0_get_cu_active_bitmap_per_sh()
6352 	int i, j, k, counter, active_cu_number = 0;  in gfx_v11_0_get_cu_info()
6362 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v11_0_get_cu_info()
6363 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v11_0_get_cu_info()
6368 			counter = 0;  in gfx_v11_0_get_cu_info()
6369 			gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v11_0_get_cu_info()
6381 			 *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}  in gfx_v11_0_get_cu_info()
6382 			 *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}  in gfx_v11_0_get_cu_info()
6383 			 *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}  in gfx_v11_0_get_cu_info()
6384 			 *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}  in gfx_v11_0_get_cu_info()
6385 			 *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}  in gfx_v11_0_get_cu_info()
6390 			cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;  in gfx_v11_0_get_cu_info()
6392 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {  in gfx_v11_0_get_cu_info()
6401 	gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v11_0_get_cu_info()
6407 	return 0;  in gfx_v11_0_get_cu_info()
6414 	.minor = 0,
6415 	.rev = 0,