48 	unsigned long flags, address, data;  in df_v3_6_get_fica()  local
51 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in df_v3_6_get_fica()
52 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in df_v3_6_get_fica()
54 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in df_v3_6_get_fica()
55 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);  in df_v3_6_get_fica()
56 	WREG32(data, ficaa_val);  in df_v3_6_get_fica()
58 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);  in df_v3_6_get_fica()
59 	ficadl_val = RREG32(data);  in df_v3_6_get_fica()
61 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);  in df_v3_6_get_fica()
62 	ficadh_val = RREG32(data);  in df_v3_6_get_fica()
64 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in df_v3_6_get_fica()
72 	unsigned long flags, address, data;  in df_v3_6_set_fica()  local
74 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in df_v3_6_set_fica()
75 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in df_v3_6_set_fica()
77 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in df_v3_6_set_fica()
78 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);  in df_v3_6_set_fica()
79 	WREG32(data, ficaa_val);  in df_v3_6_set_fica()
81 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);  in df_v3_6_set_fica()
82 	WREG32(data, ficadl_val);  in df_v3_6_set_fica()
84 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);  in df_v3_6_set_fica()
85 	WREG32(data, ficadh_val);  in df_v3_6_set_fica()
87 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in df_v3_6_set_fica()
91  * df_v3_6_perfmon_rreg - read perfmon lo and hi
100 	unsigned long flags, address, data;  in df_v3_6_perfmon_rreg()  local
102 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in df_v3_6_perfmon_rreg()
103 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in df_v3_6_perfmon_rreg()
105 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_rreg()
106 	WREG32(address, lo_addr);  in df_v3_6_perfmon_rreg()
107 	*lo_val = RREG32(data);  in df_v3_6_perfmon_rreg()
108 	WREG32(address, hi_addr);  in df_v3_6_perfmon_rreg()
109 	*hi_val = RREG32(data);  in df_v3_6_perfmon_rreg()
110 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_rreg()
114  * df_v3_6_perfmon_wreg - write to perfmon lo and hi
117  * data writes cannot occur to preserve data fabrics finite state machine.
122 	unsigned long flags, address, data;  in df_v3_6_perfmon_wreg()  local
124 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in df_v3_6_perfmon_wreg()
125 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in df_v3_6_perfmon_wreg()
127 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_wreg()
128 	WREG32(address, lo_addr);  in df_v3_6_perfmon_wreg()
129 	WREG32(data, lo_val);  in df_v3_6_perfmon_wreg()
130 	WREG32(address, hi_addr);  in df_v3_6_perfmon_wreg()
131 	WREG32(data, hi_val);  in df_v3_6_perfmon_wreg()
132 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_wreg()
140 	unsigned long flags, address, data;  in df_v3_6_perfmon_arm_with_status()  local
143 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in df_v3_6_perfmon_arm_with_status()
144 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in df_v3_6_perfmon_arm_with_status()
146 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_arm_with_status()
147 	WREG32(address, lo_addr);  in df_v3_6_perfmon_arm_with_status()
148 	WREG32(data, lo_val);  in df_v3_6_perfmon_arm_with_status()
149 	WREG32(address, hi_addr);  in df_v3_6_perfmon_arm_with_status()
150 	WREG32(data, hi_val);  in df_v3_6_perfmon_arm_with_status()
152 	WREG32(address, lo_addr);  in df_v3_6_perfmon_arm_with_status()
153 	lo_val_rb = RREG32(data);  in df_v3_6_perfmon_arm_with_status()
154 	WREG32(address, hi_addr);  in df_v3_6_perfmon_arm_with_status()
155 	hi_val_rb = RREG32(data);  in df_v3_6_perfmon_arm_with_status()
156 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in df_v3_6_perfmon_arm_with_status()
159 		return -EBUSY;  in df_v3_6_perfmon_arm_with_status()
183 		countdown -= ARM_RETRY_USEC_INTERVAL;  in df_v3_6_perfmon_arm_with_retry()
187 	return countdown > 0 ? 0 : -ETIME;  in df_v3_6_perfmon_arm_with_retry()
204 		if (adev->df_perfmon_config_assign_mask[i] == 0)  in df_v3_6_get_df_cntr_avail()
218 	adev->df.hash_status.hash_64k = false;  in df_v3_6_query_hashes()
219 	adev->df.hash_status.hash_2m = false;  in df_v3_6_query_hashes()
220 	adev->df.hash_status.hash_1g = false;  in df_v3_6_query_hashes()
222 	/* encoding for hash-enabled on Arcturus and Aldebaran */  in df_v3_6_query_hashes()
223 	if ((adev->asic_type == CHIP_ARCTURUS &&  in df_v3_6_query_hashes()
224 	     adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||  in df_v3_6_query_hashes()
225 	     (adev->asic_type == CHIP_ALDEBARAN &&  in df_v3_6_query_hashes()
226 	      adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {  in df_v3_6_query_hashes()
228 		adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,  in df_v3_6_query_hashes()
231 		adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,  in df_v3_6_query_hashes()
234 		adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,  in df_v3_6_query_hashes()
245 	ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);  in df_v3_6_sw_init()
250 		adev->df_perfmon_config_assign_mask[i] = 0;  in df_v3_6_sw_init()
258 	device_remove_file(adev->dev, &dev_attr_df_cntr_avail);  in df_v3_6_sw_fini()
280 	if (adev->asic_type == CHIP_ALDEBARAN) {  in df_v3_6_get_fb_channel_number()
297 	fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);  in df_v3_6_get_hbm_channel_number()
309 	if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {  in df_v3_6_update_medium_grain_clock_gating()
311 		adev->df.funcs->enable_broadcast_mode(adev, true);  in df_v3_6_update_medium_grain_clock_gating()
330 		adev->df.funcs->enable_broadcast_mode(adev, false);  in df_v3_6_update_medium_grain_clock_gating()
352 			adev->df_perfmon_config_assign_mask[counter_idx]);  in df_v3_6_pmc_has_counter()
356 /* get address based on counter assignment */
390 /* get read counter address */
401 /* get control counter settings i.e. address and values to set */
421 		return -ENXIO;  in df_v3_6_pmc_get_ctrl_settings()
449 		if (adev->df_perfmon_config_assign_mask[i] == 0U) {  in df_v3_6_pmc_add_cntr()
450 			adev->df_perfmon_config_assign_mask[i] =  in df_v3_6_pmc_add_cntr()
456 	return -ENOSPC;  in df_v3_6_pmc_add_cntr()
466 		return -EINVAL;  in df_v3_6_pmc_set_deferred()
469 		adev->df_perfmon_config_assign_mask[counter_idx] |=  in df_v3_6_pmc_set_deferred()
472 		adev->df_perfmon_config_assign_mask[counter_idx] &=  in df_v3_6_pmc_set_deferred()
483 			(adev->df_perfmon_config_assign_mask[counter_idx]  in df_v3_6_pmc_is_deferred()
494 		adev->df_perfmon_config_assign_mask[counter_idx] = 0ULL;  in df_v3_6_pmc_release_cntr()
520 	switch (adev->asic_type) {  in df_v3_6_pmc_start()
562 	switch (adev->asic_type) {  in df_v3_6_pmc_stop()
601 	switch (adev->asic_type) {  in df_v3_6_pmc_get_count()
664 		dev_warn(adev->dev, "DF poison setting is inconsistent(%d:%d:%d:%d)!\n",  in df_v3_6_query_ras_poison_mode()