Lines Matching +full:needs +full:- +full:hpd
72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
87 (0x13830 - 0x7030) >> 2,
94 uint32_t hpd; member
100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
156 if (crtc >= adev->mode_info.num_crtc) in dce_v6_0_vblank_get_counter()
167 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_init()
168 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_init()
176 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_fini()
177 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_fini()
181 * dce_v6_0_page_flip - pageflip callback.
197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
205 fb->pitches[0] / fb->format->cpp[0]); in dce_v6_0_page_flip()
207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v6_0_crtc_get_scanoutpos()
220 return -EINVAL; in dce_v6_0_crtc_get_scanoutpos()
229 * dce_v6_0_hpd_sense - hpd sense callback.
232 * @hpd: hpd (hotplug detect) pin
238 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_sense() argument
242 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_sense()
245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) in dce_v6_0_hpd_sense()
252 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
255 * @hpd: hpd (hotplug detect) pin
257 * Set the polarity of the hpd pin (evergreen+).
260 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_set_polarity() argument
263 bool connected = dce_v6_0_hpd_sense(adev, hpd); in dce_v6_0_hpd_set_polarity()
265 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_set_polarity()
268 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
277 * dce_v6_0_hpd_init - hpd setup callback.
281 * Setup the hpd pins used by the card (evergreen+).
282 * Enable the pin, set the polarity, and enable the hpd interrupts.
295 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_init()
298 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
300 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
302 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v6_0_hpd_init()
303 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v6_0_hpd_init()
304 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v6_0_hpd_init()
309 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
311 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
315 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
316 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
322 * dce_v6_0_hpd_fini - hpd tear down callback.
326 * Tear down the hpd pins used by the card (evergreen+).
327 * Disable the hpd interrupts.
340 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_fini()
343 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_fini()
345 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_fini()
347 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_fini()
368 switch (adev->asic_type) { in dce_v6_0_get_num_crtc()
407 struct drm_device *dev = encoder->dev; in dce_v6_0_program_fmt()
411 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt()
419 dither = amdgpu_connector->dither; in dce_v6_0_program_fmt()
423 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v6_0_program_fmt()
458 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
462 * si_get_number_of_dram_channels - get the number of dram channels
514 * dce_v6_0_dram_bandwidth - get the dram bandwidth
530 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()
532 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()
543 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
559 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()
561 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()
572 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
588 sclk.full = dfixed_const(wm->sclk); in dce_v6_0_data_return_bandwidth()
601 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
617 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
632 * dce_v6_0_available_bandwidth - get the min available bandwidth
651 * dce_v6_0_average_bandwidth - get the average available bandwidth
672 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v6_0_average_bandwidth()
674 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v6_0_average_bandwidth()
675 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
677 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
684 * dce_v6_0_latency_watermark - get the latency watermark
699 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v6_0_latency_watermark()
700 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
701 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
707 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
712 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
713 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
714 (wm->vtaps >= 5) || in dce_v6_0_latency_watermark()
715 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
721 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
723 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v6_0_latency_watermark()
726 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v6_0_latency_watermark()
728 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
735 if (line_fill_time < wm->active_time) in dce_v6_0_latency_watermark()
738 return latency + (line_fill_time - wm->active_time); in dce_v6_0_latency_watermark()
743 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
756 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
763 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
776 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
783 * dce_v6_0_check_latency_hiding - check latency hiding
793 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
794 u32 line_time = wm->active_time + wm->blank_time; in dce_v6_0_check_latency_hiding()
800 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
803 if (lb_partitions <= (wm->vtaps + 1)) in dce_v6_0_check_latency_hiding()
809 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v6_0_check_latency_hiding()
818 * dce_v6_0_program_watermarks - program display watermarks
832 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
844 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
845 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v6_0_program_watermarks()
846 (u32)mode->clock); in dce_v6_0_program_watermarks()
847 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v6_0_program_watermarks()
848 (u32)mode->clock); in dce_v6_0_program_watermarks()
856 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
862 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
863 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
866 wm_high.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
867 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
869 wm_high.blank_time = line_time - wm_high.active_time; in dce_v6_0_program_watermarks()
871 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
873 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
875 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
882 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
889 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
890 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
893 wm_low.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
894 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
896 wm_low.blank_time = line_time - wm_low.active_time; in dce_v6_0_program_watermarks()
898 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
900 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
902 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
919 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
927 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
934 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
938 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
946 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
950 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
957 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
961 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
965 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
966 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
970 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
973 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
974 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
978 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
981 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
982 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
985 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
986 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
989 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
999 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1006 * 0 - half lb in dce_v6_0_line_buffer_adjust()
1007 * 2 - whole lb, other crtc must be disabled in dce_v6_0_line_buffer_adjust()
1011 * non-linked crtcs for maximum line buffer allocation. in dce_v6_0_line_buffer_adjust()
1013 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1026 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1031 for (i = 0; i < adev->usec_timeout; i++) { in dce_v6_0_line_buffer_adjust()
1038 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1054 * dce_v6_0_bandwidth_update - program display watermarks
1068 if (!adev->mode_info.mode_config_initialized) in dce_v6_0_bandwidth_update()
1073 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_bandwidth_update()
1074 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1077 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { in dce_v6_0_bandwidth_update()
1078 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1079 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1080 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1081 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1082 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1083 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1092 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_connected_pins()
1093 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, in dce_v6_0_audio_get_connected_pins()
1097 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_get_connected_pins()
1099 adev->mode_info.audio.pin[i].connected = true; in dce_v6_0_audio_get_connected_pins()
1110 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_pin()
1111 if (adev->mode_info.audio.pin[i].connected) in dce_v6_0_audio_get_pin()
1112 return &adev->mode_info.audio.pin[i]; in dce_v6_0_audio_get_pin()
1120 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_audio_select_pin()
1122 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_select_pin()
1124 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v6_0_audio_select_pin()
1127 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce_v6_0_audio_select_pin()
1129 dig->afmt->pin->id)); in dce_v6_0_audio_select_pin()
1135 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_latency_fields()
1138 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_latency_fields()
1147 if (connector->encoder == encoder) { in dce_v6_0_audio_write_latency_fields()
1159 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_audio_write_latency_fields()
1162 if (connector->latency_present[interlace]) { in dce_v6_0_audio_write_latency_fields()
1164 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1166 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1173 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_latency_fields()
1179 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_speaker_allocation()
1182 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_speaker_allocation()
1192 if (connector->encoder == encoder) { in dce_v6_0_audio_write_speaker_allocation()
1211 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1218 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) in dce_v6_0_audio_write_speaker_allocation()
1232 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1240 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_sad_regs()
1243 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_sad_regs()
1267 if (connector->encoder == encoder) { in dce_v6_0_audio_write_sad_regs()
1288 int max_channels = -1; in dce_v6_0_audio_write_sad_regs()
1294 if (sad->format == eld_reg_to_type[i][1]) { in dce_v6_0_audio_write_sad_regs()
1295 if (sad->channels > max_channels) { in dce_v6_0_audio_write_sad_regs()
1297 MAX_CHANNELS, sad->channels); in dce_v6_0_audio_write_sad_regs()
1299 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v6_0_audio_write_sad_regs()
1301 SUPPORTED_FREQUENCIES, sad->freq); in dce_v6_0_audio_write_sad_regs()
1302 max_channels = sad->channels; in dce_v6_0_audio_write_sad_regs()
1305 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v6_0_audio_write_sad_regs()
1306 stereo_freqs |= sad->freq; in dce_v6_0_audio_write_sad_regs()
1314 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v6_0_audio_write_sad_regs()
1328 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v6_0_audio_enable()
1334 (0x1780 - 0x1780),
1335 (0x1786 - 0x1780),
1336 (0x178c - 0x1780),
1337 (0x1792 - 0x1780),
1338 (0x1798 - 0x1780),
1339 (0x179d - 0x1780),
1340 (0x17a4 - 0x1780),
1350 adev->mode_info.audio.enabled = true; in dce_v6_0_audio_init()
1352 switch (adev->asic_type) { in dce_v6_0_audio_init()
1357 adev->mode_info.audio.num_pins = 6; in dce_v6_0_audio_init()
1360 adev->mode_info.audio.num_pins = 2; in dce_v6_0_audio_init()
1364 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_init()
1365 adev->mode_info.audio.pin[i].channels = -1; in dce_v6_0_audio_init()
1366 adev->mode_info.audio.pin[i].rate = -1; in dce_v6_0_audio_init()
1367 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v6_0_audio_init()
1368 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v6_0_audio_init()
1369 adev->mode_info.audio.pin[i].category_code = 0; in dce_v6_0_audio_init()
1370 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_init()
1371 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v6_0_audio_init()
1372 adev->mode_info.audio.pin[i].id = i; in dce_v6_0_audio_init()
1373 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_init()
1386 if (!adev->mode_info.audio.enabled) in dce_v6_0_audio_fini()
1389 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v6_0_audio_fini()
1390 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_fini()
1392 adev->mode_info.audio.enabled = false; in dce_v6_0_audio_fini()
1397 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_vbi_packet()
1400 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_vbi_packet()
1403 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_vbi_packet()
1407 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_vbi_packet()
1413 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_acr()
1417 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_acr()
1420 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1424 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1426 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1428 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1429 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1431 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1433 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1435 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1436 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1438 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1440 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1442 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1443 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1445 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1451 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_avi_infoframe()
1454 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_avi_infoframe()
1475 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1477 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1479 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1481 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1484 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_set_avi_infoframe()
1488 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_avi_infoframe()
1493 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_dto()
1495 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto()
1507 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1527 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_packet()
1530 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_packet()
1533 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1535 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1537 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1539 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1541 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1543 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1545 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1552 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1554 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1556 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1558 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1561 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1563 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1566 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1571 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_mute()
1574 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_mute()
1577 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); in dce_v6_0_audio_set_mute()
1579 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); in dce_v6_0_audio_set_mute()
1584 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_hdmi_enable()
1587 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_hdmi_enable()
1591 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1596 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1598 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1600 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1602 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1604 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1606 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1611 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1613 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1615 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1621 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_dp_enable()
1624 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_dp_enable()
1628 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1630 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1632 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1634 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1636 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1641 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1643 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); in dce_v6_0_audio_dp_enable()
1650 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_setmode()
1653 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_setmode()
1660 if (!dig || !dig->afmt) in dce_v6_0_afmt_setmode()
1665 if (connector->encoder == encoder) { in dce_v6_0_afmt_setmode()
1677 if (!dig->afmt->enabled) in dce_v6_0_afmt_setmode()
1680 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); in dce_v6_0_afmt_setmode()
1681 if (!dig->afmt->pin) in dce_v6_0_afmt_setmode()
1684 if (encoder->crtc) { in dce_v6_0_afmt_setmode()
1685 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode()
1686 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1690 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_setmode()
1697 dce_v6_0_audio_set_dto(encoder, mode->clock); in dce_v6_0_afmt_setmode()
1699 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); in dce_v6_0_afmt_setmode()
1701 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); in dce_v6_0_afmt_setmode()
1714 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); in dce_v6_0_afmt_setmode()
1719 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_enable()
1722 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_enable()
1724 if (!dig || !dig->afmt) in dce_v6_0_afmt_enable()
1728 if (enable && dig->afmt->enabled) in dce_v6_0_afmt_enable()
1731 if (!enable && !dig->afmt->enabled) in dce_v6_0_afmt_enable()
1734 if (!enable && dig->afmt->pin) { in dce_v6_0_afmt_enable()
1735 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_enable()
1736 dig->afmt->pin = NULL; in dce_v6_0_afmt_enable()
1739 dig->afmt->enabled = enable; in dce_v6_0_afmt_enable()
1742 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v6_0_afmt_enable()
1749 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v6_0_afmt_init()
1750 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_init()
1753 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_init()
1754 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v6_0_afmt_init()
1755 if (adev->mode_info.afmt[i]) { in dce_v6_0_afmt_init()
1756 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v6_0_afmt_init()
1757 adev->mode_info.afmt[i]->id = i; in dce_v6_0_afmt_init()
1760 kfree(adev->mode_info.afmt[j]); in dce_v6_0_afmt_init()
1761 adev->mode_info.afmt[j] = NULL; in dce_v6_0_afmt_init()
1764 return -ENOMEM; in dce_v6_0_afmt_init()
1774 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_fini()
1775 kfree(adev->mode_info.afmt[i]); in dce_v6_0_afmt_fini()
1776 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_fini()
1793 struct drm_device *dev = crtc->dev; in dce_v6_0_vga_enable()
1797 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1798 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1804 struct drm_device *dev = crtc->dev; in dce_v6_0_grph_enable()
1807 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1815 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_do_set_base()
1828 if (!atomic && !crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
1836 target_fb = crtc->primary->fb; in dce_v6_0_crtc_do_set_base()
1841 obj = target_fb->obj[0]; in dce_v6_0_crtc_do_set_base()
1851 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1859 switch (target_fb->format->format) { in dce_v6_0_crtc_do_set_base()
1910 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1920 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1935 &target_fb->format->format); in dce_v6_0_crtc_do_set_base()
1936 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1966 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1968 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1970 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1972 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1974 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1976 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
1977 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
1984 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1991 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1992 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1993 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1994 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1995 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
1996 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
1998 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v6_0_crtc_do_set_base()
1999 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2003 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2004 target_fb->height); in dce_v6_0_crtc_do_set_base()
2007 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2009 viewport_w = crtc->mode.hdisplay; in dce_v6_0_crtc_do_set_base()
2010 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v6_0_crtc_do_set_base()
2012 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2016 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2018 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
2019 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v6_0_crtc_do_set_base()
2037 struct drm_device *dev = crtc->dev; in dce_v6_0_set_interleave()
2041 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_set_interleave()
2042 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2045 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2052 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_load_lut()
2057 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2059 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2062 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2064 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2066 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2070 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2072 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2073 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2074 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2076 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2077 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2078 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2080 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2081 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2083 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2084 r = crtc->gamma_store; in dce_v6_0_crtc_load_lut()
2085 g = r + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2086 b = g + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2088 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2094 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2099 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2102 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2105 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2109 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2117 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_pick_dig_encoder()
2119 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_pick_dig_encoder()
2121 return dig->linkb ? 1 : 0; in dce_v6_0_pick_dig_encoder()
2123 return dig->linkb ? 3 : 2; in dce_v6_0_pick_dig_encoder()
2125 return dig->linkb ? 5 : 4; in dce_v6_0_pick_dig_encoder()
2129 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v6_0_pick_dig_encoder()
2135 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2140 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2152 struct drm_device *dev = crtc->dev; in dce_v6_0_pick_pll()
2157 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2158 if (adev->clock.dp_extclk) in dce_v6_0_pick_pll()
2182 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_lock_cursor()
2186 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2191 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2197 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_hide_cursor()
2199 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2209 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_show_cursor()
2211 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2212 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2213 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2214 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2216 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2227 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_cursor_move_locked()
2230 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2232 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2233 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2236 x += crtc->x; in dce_v6_0_cursor_move_locked()
2237 y += crtc->y; in dce_v6_0_cursor_move_locked()
2238 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v6_0_cursor_move_locked()
2241 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2245 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2249 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2250 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2251 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2252 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2289 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2290 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2292 return -EINVAL; in dce_v6_0_crtc_cursor_set2()
2297 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2298 return -ENOENT; in dce_v6_0_crtc_cursor_set2()
2315 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2319 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2320 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2321 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2322 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2325 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2326 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2330 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2331 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2332 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2333 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2340 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2341 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2347 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2350 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2358 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2361 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2362 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2401 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_dpms()
2408 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2413 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2414 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v6_0_crtc_dpms()
2415 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v6_0_crtc_dpms()
2423 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2426 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2451 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_disable()
2457 if (crtc->primary->fb) { in dce_v6_0_crtc_disable()
2461 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v6_0_crtc_disable()
2475 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_crtc_disable()
2476 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2477 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
2478 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2479 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2487 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2491 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2498 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2499 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2500 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2501 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2511 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2512 return -EINVAL; in dce_v6_0_crtc_mode_set()
2521 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2532 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_mode_fixup()
2536 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_crtc_mode_fixup()
2537 if (encoder->crtc == crtc) { in dce_v6_0_crtc_mode_fixup()
2538 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2539 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2543 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2544 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2545 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2553 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2554 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
2555 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2556 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2594 return -ENOMEM; in dce_v6_0_crtc_init()
2596 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2598 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2599 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2600 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2602 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2603 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2604 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2605 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2607 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2609 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2610 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2611 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2612 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2613 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
2622 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; in dce_v6_0_early_init()
2623 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; in dce_v6_0_early_init()
2627 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); in dce_v6_0_early_init()
2629 switch (adev->asic_type) { in dce_v6_0_early_init()
2633 adev->mode_info.num_hpd = 6; in dce_v6_0_early_init()
2634 adev->mode_info.num_dig = 6; in dce_v6_0_early_init()
2637 adev->mode_info.num_hpd = 2; in dce_v6_0_early_init()
2638 adev->mode_info.num_dig = 2; in dce_v6_0_early_init()
2641 return -EINVAL; in dce_v6_0_early_init()
2655 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2656 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v6_0_sw_init()
2662 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v6_0_sw_init()
2667 /* HPD hotplug */ in dce_v6_0_sw_init()
2668 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); in dce_v6_0_sw_init()
2672 adev->mode_info.mode_config_initialized = true; in dce_v6_0_sw_init()
2674 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v6_0_sw_init()
2675 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v6_0_sw_init()
2676 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2677 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2678 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v6_0_sw_init()
2679 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v6_0_sw_init()
2680 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v6_0_sw_init()
2686 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2687 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2690 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2700 return -EINVAL; in dce_v6_0_sw_init()
2711 /* Disable vblank IRQs aggressively for power-saving */ in dce_v6_0_sw_init()
2713 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v6_0_sw_init()
2715 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v6_0_sw_init()
2719 /* Pre-DCE11 */ in dce_v6_0_sw_init()
2720 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v6_0_sw_init()
2732 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v6_0_sw_fini()
2740 adev->mode_info.mode_config_initialized = false; in dce_v6_0_sw_fini()
2754 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v6_0_hw_init()
2756 /* initialize hpd */ in dce_v6_0_hw_init()
2759 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_init()
2760 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_init()
2775 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_fini()
2776 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_fini()
2781 flush_delayed_work(&adev->hotplug_work); in dce_v6_0_hw_fini()
2794 adev->mode_info.bl_level = in dce_v6_0_suspend()
2806 adev->mode_info.bl_level); in dce_v6_0_resume()
2811 if (adev->mode_info.bl_encoder) { in dce_v6_0_resume()
2813 adev->mode_info.bl_encoder); in dce_v6_0_resume()
2814 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v6_0_resume()
2835 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); in dce_v6_0_soft_reset()
2845 if (crtc >= adev->mode_info.num_crtc) { in dce_v6_0_set_crtc_vblank_interrupt_state()
2904 if (type >= adev->mode_info.num_hpd) { in dce_v6_0_set_hpd_interrupt_state()
2979 unsigned crtc = entry->src_id - 1; in dce_v6_0_crtc_irq()
2984 switch (entry->src_data[0]) { in dce_v6_0_crtc_irq()
3005 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_crtc_irq()
3019 if (type >= adev->mode_info.num_crtc) { in dce_v6_0_set_pageflip_interrupt_state()
3021 return -EINVAL; in dce_v6_0_set_pageflip_interrupt_state()
3044 crtc_id = (entry->src_id - 8) >> 1; in dce_v6_0_pageflip_irq()
3045 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3047 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v6_0_pageflip_irq()
3049 return -EINVAL; in dce_v6_0_pageflip_irq()
3061 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3062 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3063 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v6_0_pageflip_irq()
3064 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v6_0_pageflip_irq()
3066 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3068 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3073 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3074 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3077 if (works->event) in dce_v6_0_pageflip_irq()
3078 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3080 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3082 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()
3083 schedule_work(&works->unpin_work); in dce_v6_0_pageflip_irq()
3093 unsigned hpd; in dce_v6_0_hpd_irq() local
3095 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_irq()
3096 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_hpd_irq()
3100 hpd = entry->src_data[0]; in dce_v6_0_hpd_irq()
3101 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3102 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
3105 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_irq()
3107 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_irq()
3108 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v6_0_hpd_irq()
3109 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v6_0_hpd_irq()
3154 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v6_0_encoder_mode_set()
3160 dce_v6_0_set_interleave(encoder->crtc, mode); in dce_v6_0_encoder_mode_set()
3171 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_encoder_prepare()
3175 if ((amdgpu_encoder->active_device & in dce_v6_0_encoder_prepare()
3179 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_prepare()
3181 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); in dce_v6_0_encoder_prepare()
3182 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v6_0_encoder_prepare()
3183 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v6_0_encoder_prepare()
3193 if (amdgpu_connector->router.cd_valid) in dce_v6_0_encoder_prepare()
3197 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v6_0_encoder_prepare()
3211 struct drm_device *dev = encoder->dev; in dce_v6_0_encoder_commit()
3231 dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_disable()
3232 dig->dig_encoder = -1; in dce_v6_0_encoder_disable()
3234 amdgpu_encoder->active_device = 0; in dce_v6_0_encoder_disable()
3306 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_destroy()
3308 kfree(amdgpu_encoder->enc_priv); in dce_v6_0_encoder_destroy()
3327 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_encoder_add()
3329 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v6_0_encoder_add()
3330 amdgpu_encoder->devices |= supported_device; in dce_v6_0_encoder_add()
3341 encoder = &amdgpu_encoder->base; in dce_v6_0_encoder_add()
3342 switch (adev->mode_info.num_crtc) { in dce_v6_0_encoder_add()
3344 encoder->possible_crtcs = 0x1; in dce_v6_0_encoder_add()
3348 encoder->possible_crtcs = 0x3; in dce_v6_0_encoder_add()
3351 encoder->possible_crtcs = 0xf; in dce_v6_0_encoder_add()
3354 encoder->possible_crtcs = 0x3f; in dce_v6_0_encoder_add()
3358 amdgpu_encoder->enc_priv = NULL; in dce_v6_0_encoder_add()
3359 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v6_0_encoder_add()
3360 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v6_0_encoder_add()
3361 amdgpu_encoder->devices = supported_device; in dce_v6_0_encoder_add()
3362 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v6_0_encoder_add()
3363 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v6_0_encoder_add()
3364 amdgpu_encoder->is_ext_encoder = false; in dce_v6_0_encoder_add()
3365 amdgpu_encoder->caps = caps; in dce_v6_0_encoder_add()
3367 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_encoder_add()
3379 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v6_0_encoder_add()
3380 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v6_0_encoder_add()
3383 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3384 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v6_0_encoder_add()
3387 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3391 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3405 amdgpu_encoder->is_ext_encoder = true; in dce_v6_0_encoder_add()
3406 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_add()
3409 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v6_0_encoder_add()
3436 adev->mode_info.funcs = &dce_v6_0_display_funcs; in dce_v6_0_set_display_funcs()
3456 if (adev->mode_info.num_crtc > 0) in dce_v6_0_set_irq_funcs()
3457 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3459 adev->crtc_irq.num_types = 0; in dce_v6_0_set_irq_funcs()
3460 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; in dce_v6_0_set_irq_funcs()
3462 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3463 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; in dce_v6_0_set_irq_funcs()
3465 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v6_0_set_irq_funcs()
3466 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; in dce_v6_0_set_irq_funcs()