Lines Matching +full:needs +full:- +full:hpd
93 uint32_t hpd; member
99 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
124 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
164 switch (adev->asic_type) { in dce_v11_0_init_golden_registers()
201 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
204 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
214 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
217 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
222 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in dce_v11_0_vblank_get_counter()
233 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_init()
234 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_init()
242 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_fini()
243 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_fini()
247 * dce_v11_0_page_flip - pageflip callback.
260 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip()
261 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v11_0_page_flip()
265 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
268 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
270 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
271 fb->pitches[0] / fb->format->cpp[0]); in dce_v11_0_page_flip()
273 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
276 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
279 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
285 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v11_0_crtc_get_scanoutpos()
286 return -EINVAL; in dce_v11_0_crtc_get_scanoutpos()
295 * dce_v11_0_hpd_sense - hpd sense callback.
298 * @hpd: hpd (hotplug detect) pin
304 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_sense() argument
308 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_sense()
311 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v11_0_hpd_sense()
319 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
322 * @hpd: hpd (hotplug detect) pin
324 * Set the polarity of the hpd pin (evergreen+).
327 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_set_polarity() argument
330 bool connected = dce_v11_0_hpd_sense(adev, hpd); in dce_v11_0_hpd_set_polarity()
332 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_set_polarity()
335 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
344 * dce_v11_0_hpd_init - hpd setup callback.
348 * Setup the hpd pins used by the card (evergreen+).
349 * Enable the pin, set the polarity, and enable the hpd interrupts.
362 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_init()
365 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v11_0_hpd_init()
366 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v11_0_hpd_init()
367 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v11_0_hpd_init()
372 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
374 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
378 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
380 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
382 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
389 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
391 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
392 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
398 * dce_v11_0_hpd_fini - hpd tear down callback.
402 * Tear down the hpd pins used by the card (evergreen+).
403 * Disable the hpd interrupts.
416 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_fini()
419 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_fini()
421 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_fini()
423 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_fini()
439 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
448 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
489 switch (adev->asic_type) { in dce_v11_0_get_num_crtc()
536 struct drm_device *dev = encoder->dev; in dce_v11_0_program_fmt()
539 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_program_fmt()
548 dither = amdgpu_connector->dither; in dce_v11_0_program_fmt()
552 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v11_0_program_fmt()
556 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v11_0_program_fmt()
557 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v11_0_program_fmt()
607 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
613 * dce_v11_0_line_buffer_adjust - Set up the line buffer
629 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust()
638 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
639 if (mode->crtc_hdisplay < 1920) { in dce_v11_0_line_buffer_adjust()
642 } else if (mode->crtc_hdisplay < 2560) { in dce_v11_0_line_buffer_adjust()
645 } else if (mode->crtc_hdisplay < 4096) { in dce_v11_0_line_buffer_adjust()
647 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
651 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
658 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
660 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
666 for (i = 0; i < adev->usec_timeout; i++) { in dce_v11_0_line_buffer_adjust()
673 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
690 * cik_get_number_of_dram_channels - get the number of dram channels
742 * dce_v11_0_dram_bandwidth - get the dram bandwidth
758 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()
760 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()
771 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
787 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()
789 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()
800 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
816 sclk.full = dfixed_const(wm->sclk); in dce_v11_0_data_return_bandwidth()
829 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
845 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v11_0_dmif_request_bandwidth()
860 * dce_v11_0_available_bandwidth - get the min available bandwidth
879 * dce_v11_0_average_bandwidth - get the average available bandwidth
900 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v11_0_average_bandwidth()
902 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v11_0_average_bandwidth()
903 src_width.full = dfixed_const(wm->src_width); in dce_v11_0_average_bandwidth()
905 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()
912 * dce_v11_0_latency_watermark - get the latency watermark
927 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v11_0_latency_watermark()
928 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
929 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
935 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
940 if ((wm->vsc.full > a.full) || in dce_v11_0_latency_watermark()
941 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
942 (wm->vtaps >= 5) || in dce_v11_0_latency_watermark()
943 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v11_0_latency_watermark()
949 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
951 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v11_0_latency_watermark()
954 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v11_0_latency_watermark()
956 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v11_0_latency_watermark()
963 if (line_fill_time < wm->active_time) in dce_v11_0_latency_watermark()
966 return latency + (line_fill_time - wm->active_time); in dce_v11_0_latency_watermark()
971 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
984 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
991 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1004 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1011 * dce_v11_0_check_latency_hiding - check latency hiding
1021 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1022 u32 line_time = wm->active_time + wm->blank_time; in dce_v11_0_check_latency_hiding()
1028 if (wm->vsc.full > a.full) in dce_v11_0_check_latency_hiding()
1031 if (lb_partitions <= (wm->vtaps + 1)) in dce_v11_0_check_latency_hiding()
1037 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v11_0_check_latency_hiding()
1046 * dce_v11_0_program_watermarks - program display watermarks
1060 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v11_0_program_watermarks()
1067 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1068 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v11_0_program_watermarks()
1069 (u32)mode->clock); in dce_v11_0_program_watermarks()
1070 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v11_0_program_watermarks()
1071 (u32)mode->clock); in dce_v11_0_program_watermarks()
1075 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1081 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1082 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1085 wm_high.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1086 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1088 wm_high.blank_time = line_time - wm_high.active_time; in dce_v11_0_program_watermarks()
1090 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1092 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1094 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1109 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1114 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1120 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1121 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1124 wm_low.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1125 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1127 wm_low.blank_time = line_time - wm_low.active_time; in dce_v11_0_program_watermarks()
1129 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1131 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1133 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1148 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1151 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
1155 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1157 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1158 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1161 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1164 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1165 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1168 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1170 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
1173 amdgpu_crtc->line_time = line_time; in dce_v11_0_program_watermarks()
1174 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v11_0_program_watermarks()
1175 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v11_0_program_watermarks()
1177 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v11_0_program_watermarks()
1181 * dce_v11_0_bandwidth_update - program display watermarks
1196 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1197 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v11_0_bandwidth_update()
1200 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1201 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v11_0_bandwidth_update()
1202 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1203 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v11_0_bandwidth_update()
1213 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_connected_pins()
1214 offset = adev->mode_info.audio.pin[i].offset; in dce_v11_0_audio_get_connected_pins()
1220 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_get_connected_pins()
1222 adev->mode_info.audio.pin[i].connected = true; in dce_v11_0_audio_get_connected_pins()
1232 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_pin()
1233 if (adev->mode_info.audio.pin[i].connected) in dce_v11_0_audio_get_pin()
1234 return &adev->mode_info.audio.pin[i]; in dce_v11_0_audio_get_pin()
1242 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_afmt_audio_select_pin()
1244 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_audio_select_pin()
1247 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_afmt_audio_select_pin()
1250 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1251 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1252 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1258 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_latency_fields()
1261 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_latency_fields()
1268 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_latency_fields()
1273 if (connector->encoder == encoder) { in dce_v11_0_audio_write_latency_fields()
1285 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_audio_write_latency_fields()
1287 if (connector->latency_present[interlace]) { in dce_v11_0_audio_write_latency_fields()
1289 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1291 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1298 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_latency_fields()
1304 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_speaker_allocation()
1307 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_speaker_allocation()
1315 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_speaker_allocation()
1320 if (connector->encoder == encoder) { in dce_v11_0_audio_write_speaker_allocation()
1339 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1352 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1360 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_sad_regs()
1363 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_sad_regs()
1385 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_sad_regs()
1390 if (connector->encoder == encoder) { in dce_v11_0_audio_write_sad_regs()
1412 int max_channels = -1; in dce_v11_0_audio_write_sad_regs()
1418 if (sad->format == eld_reg_to_type[i][1]) { in dce_v11_0_audio_write_sad_regs()
1419 if (sad->channels > max_channels) { in dce_v11_0_audio_write_sad_regs()
1421 MAX_CHANNELS, sad->channels); in dce_v11_0_audio_write_sad_regs()
1423 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v11_0_audio_write_sad_regs()
1425 SUPPORTED_FREQUENCIES, sad->freq); in dce_v11_0_audio_write_sad_regs()
1426 max_channels = sad->channels; in dce_v11_0_audio_write_sad_regs()
1429 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v11_0_audio_write_sad_regs()
1430 stereo_freqs |= sad->freq; in dce_v11_0_audio_write_sad_regs()
1438 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1451 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v11_0_audio_enable()
1474 adev->mode_info.audio.enabled = true; in dce_v11_0_audio_init()
1476 switch (adev->asic_type) { in dce_v11_0_audio_init()
1479 adev->mode_info.audio.num_pins = 7; in dce_v11_0_audio_init()
1483 adev->mode_info.audio.num_pins = 8; in dce_v11_0_audio_init()
1487 adev->mode_info.audio.num_pins = 6; in dce_v11_0_audio_init()
1490 return -EINVAL; in dce_v11_0_audio_init()
1493 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_init()
1494 adev->mode_info.audio.pin[i].channels = -1; in dce_v11_0_audio_init()
1495 adev->mode_info.audio.pin[i].rate = -1; in dce_v11_0_audio_init()
1496 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v11_0_audio_init()
1497 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v11_0_audio_init()
1498 adev->mode_info.audio.pin[i].category_code = 0; in dce_v11_0_audio_init()
1499 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_init()
1500 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v11_0_audio_init()
1501 adev->mode_info.audio.pin[i].id = i; in dce_v11_0_audio_init()
1504 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_init()
1517 if (!adev->mode_info.audio.enabled) in dce_v11_0_audio_fini()
1520 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v11_0_audio_fini()
1521 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_fini()
1523 adev->mode_info.audio.enabled = false; in dce_v11_0_audio_fini()
1531 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_ACR()
1535 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_ACR()
1538 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1540 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1541 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1543 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1545 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1547 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1548 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1550 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1552 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1554 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1555 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1557 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1567 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_avi_infoframe()
1570 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_avi_infoframe()
1574 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1576 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1578 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1580 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1586 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_set_dto()
1589 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_set_dto()
1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_audio_set_dto()
1595 if (!dig || !dig->afmt) in dce_v11_0_audio_set_dto()
1605 amdgpu_crtc->crtc_id); in dce_v11_0_audio_set_dto()
1617 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_setmode()
1620 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_setmode()
1628 if (!dig || !dig->afmt) in dce_v11_0_afmt_setmode()
1632 if (!dig->afmt->enabled) in dce_v11_0_afmt_setmode()
1636 if (encoder->crtc) { in dce_v11_0_afmt_setmode()
1637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_afmt_setmode()
1638 bpc = amdgpu_crtc->bpc; in dce_v11_0_afmt_setmode()
1642 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); in dce_v11_0_afmt_setmode()
1643 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_setmode()
1645 dce_v11_0_audio_set_dto(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1647 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1649 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1651 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v11_0_afmt_setmode()
1653 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1663 connector->name, bpc); in dce_v11_0_afmt_setmode()
1669 connector->name); in dce_v11_0_afmt_setmode()
1675 connector->name); in dce_v11_0_afmt_setmode()
1678 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1680 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1684 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1686 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1691 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1693 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1696 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1698 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1701 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1703 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v11_0_afmt_setmode()
1705 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1710 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1712 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1715 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1717 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1726 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1728 dce_v11_0_afmt_update_ACR(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1730 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1732 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1734 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1736 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1738 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1745 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1749 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v11_0_afmt_setmode()
1770 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1775 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1777 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1779 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1781 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1784 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1786 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v11_0_afmt_setmode()
1787 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v11_0_afmt_setmode()
1788 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1789 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1792 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); in dce_v11_0_afmt_setmode()
1797 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_enable()
1800 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_enable()
1802 if (!dig || !dig->afmt) in dce_v11_0_afmt_enable()
1806 if (enable && dig->afmt->enabled) in dce_v11_0_afmt_enable()
1808 if (!enable && !dig->afmt->enabled) in dce_v11_0_afmt_enable()
1811 if (!enable && dig->afmt->pin) { in dce_v11_0_afmt_enable()
1812 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_enable()
1813 dig->afmt->pin = NULL; in dce_v11_0_afmt_enable()
1816 dig->afmt->enabled = enable; in dce_v11_0_afmt_enable()
1819 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v11_0_afmt_enable()
1826 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v11_0_afmt_init()
1827 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_init()
1830 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_init()
1831 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v11_0_afmt_init()
1832 if (adev->mode_info.afmt[i]) { in dce_v11_0_afmt_init()
1833 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v11_0_afmt_init()
1834 adev->mode_info.afmt[i]->id = i; in dce_v11_0_afmt_init()
1838 kfree(adev->mode_info.afmt[j]); in dce_v11_0_afmt_init()
1839 adev->mode_info.afmt[j] = NULL; in dce_v11_0_afmt_init()
1841 return -ENOMEM; in dce_v11_0_afmt_init()
1851 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_fini()
1852 kfree(adev->mode_info.afmt[i]); in dce_v11_0_afmt_fini()
1853 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_fini()
1870 struct drm_device *dev = crtc->dev; in dce_v11_0_vga_enable()
1874 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v11_0_vga_enable()
1876 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v11_0_vga_enable()
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v11_0_vga_enable()
1884 struct drm_device *dev = crtc->dev; in dce_v11_0_grph_enable()
1888 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable()
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable()
1898 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_do_set_base()
1912 if (!atomic && !crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
1920 target_fb = crtc->primary->fb; in dce_v11_0_crtc_do_set_base()
1925 obj = target_fb->obj[0]; in dce_v11_0_crtc_do_set_base()
1935 return -EINVAL; in dce_v11_0_crtc_do_set_base()
1945 switch (target_fb->format->format) { in dce_v11_0_crtc_do_set_base()
2002 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2013 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2029 &target_fb->format->format); in dce_v11_0_crtc_do_set_base()
2030 return -EINVAL; in dce_v11_0_crtc_do_set_base()
2066 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2069 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2071 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2073 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2075 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2077 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2079 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()
2080 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
2087 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2092 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2097 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2098 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2099 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2100 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2101 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v11_0_crtc_do_set_base()
2102 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v11_0_crtc_do_set_base()
2104 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v11_0_crtc_do_set_base()
2105 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v11_0_crtc_do_set_base()
2109 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2110 target_fb->height); in dce_v11_0_crtc_do_set_base()
2114 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2116 viewport_w = crtc->mode.hdisplay; in dce_v11_0_crtc_do_set_base()
2117 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v11_0_crtc_do_set_base()
2118 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2122 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2124 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
2125 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v11_0_crtc_do_set_base()
2142 struct drm_device *dev = crtc->dev; in dce_v11_0_set_interleave()
2147 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2148 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_set_interleave()
2152 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2158 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_load_lut()
2164 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v11_0_crtc_load_lut()
2166 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2168 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2170 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2172 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2174 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2176 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2178 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2180 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2181 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2182 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2184 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2185 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2186 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2188 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2189 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v11_0_crtc_load_lut()
2191 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2192 r = crtc->gamma_store; in dce_v11_0_crtc_load_lut()
2193 g = r + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2194 b = g + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2196 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_load_lut()
2202 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2206 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2208 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2210 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2212 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2214 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2216 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2218 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2221 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2222 /* XXX this only needs to be programmed once per crtc at startup, in dce_v11_0_crtc_load_lut()
2225 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2227 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2233 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_dig_encoder()
2235 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_dig_encoder()
2237 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2242 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2247 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2254 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_dig_encoder()
2260 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2276 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2278 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2284 struct drm_device *dev = crtc->dev; in dce_v11_0_pick_pll()
2289 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_pick_pll()
2290 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_pick_pll()
2291 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_pick_pll()
2292 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_pick_pll()
2294 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_pick_pll()
2295 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_pll()
2297 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_pick_pll()
2300 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_pll()
2302 if (dig->linkb) in dce_v11_0_pick_pll()
2307 if (dig->linkb) in dce_v11_0_pick_pll()
2312 if (dig->linkb) in dce_v11_0_pick_pll()
2317 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_pll()
2322 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v11_0_pick_pll()
2323 if (adev->clock.dp_extclk) in dce_v11_0_pick_pll()
2341 if (adev->flags & AMD_IS_APU) { in dce_v11_0_pick_pll()
2363 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_lock_cursor()
2367 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
2372 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v11_0_lock_cursor()
2378 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_hide_cursor()
2381 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2383 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2389 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_show_cursor()
2392 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2393 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2394 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2395 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2397 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2400 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
2407 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_cursor_move_locked()
2410 amdgpu_crtc->cursor_x = x; in dce_v11_0_cursor_move_locked()
2411 amdgpu_crtc->cursor_y = y; in dce_v11_0_cursor_move_locked()
2414 x += crtc->x; in dce_v11_0_cursor_move_locked()
2415 y += crtc->y; in dce_v11_0_cursor_move_locked()
2416 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v11_0_cursor_move_locked()
2419 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v11_0_cursor_move_locked()
2423 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v11_0_cursor_move_locked()
2427 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v11_0_cursor_move_locked()
2428 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v11_0_cursor_move_locked()
2429 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked()
2430 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v11_0_cursor_move_locked()
2467 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v11_0_crtc_cursor_set2()
2468 (height > amdgpu_crtc->max_cursor_height)) { in dce_v11_0_crtc_cursor_set2()
2470 return -EINVAL; in dce_v11_0_crtc_cursor_set2()
2475 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v11_0_crtc_cursor_set2()
2476 return -ENOENT; in dce_v11_0_crtc_cursor_set2()
2493 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v11_0_crtc_cursor_set2()
2497 if (width != amdgpu_crtc->cursor_width || in dce_v11_0_crtc_cursor_set2()
2498 height != amdgpu_crtc->cursor_height || in dce_v11_0_crtc_cursor_set2()
2499 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v11_0_crtc_cursor_set2()
2500 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v11_0_crtc_cursor_set2()
2503 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v11_0_crtc_cursor_set2()
2504 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v11_0_crtc_cursor_set2()
2508 amdgpu_crtc->cursor_width = width; in dce_v11_0_crtc_cursor_set2()
2509 amdgpu_crtc->cursor_height = height; in dce_v11_0_crtc_cursor_set2()
2510 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v11_0_crtc_cursor_set2()
2511 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v11_0_crtc_cursor_set2()
2518 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_crtc_cursor_set2()
2519 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2525 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2528 amdgpu_crtc->cursor_bo = obj; in dce_v11_0_crtc_cursor_set2()
2536 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_cursor_reset()
2539 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v11_0_cursor_reset()
2540 amdgpu_crtc->cursor_y); in dce_v11_0_cursor_reset()
2580 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_dpms()
2587 amdgpu_crtc->enabled = true; in dce_v11_0_crtc_dpms()
2594 amdgpu_crtc->crtc_id); in dce_v11_0_crtc_dpms()
2595 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v11_0_crtc_dpms()
2596 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v11_0_crtc_dpms()
2604 if (amdgpu_crtc->enabled) { in dce_v11_0_crtc_dpms()
2610 amdgpu_crtc->enabled = false; in dce_v11_0_crtc_dpms()
2634 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_disable()
2640 if (crtc->primary->fb) { in dce_v11_0_crtc_disable()
2644 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v11_0_crtc_disable()
2658 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_crtc_disable()
2659 if (adev->mode_info.crtcs[i] && in dce_v11_0_crtc_disable()
2660 adev->mode_info.crtcs[i]->enabled && in dce_v11_0_crtc_disable()
2661 i != amdgpu_crtc->crtc_id && in dce_v11_0_crtc_disable()
2662 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable()
2670 switch (amdgpu_crtc->pll_id) { in dce_v11_0_crtc_disable()
2675 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2685 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2692 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_disable()
2693 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_disable()
2694 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_disable()
2695 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_disable()
2704 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_set()
2707 if (!amdgpu_crtc->adjusted_clock) in dce_v11_0_crtc_mode_set()
2708 return -EINVAL; in dce_v11_0_crtc_mode_set()
2710 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_crtc_mode_set()
2711 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_crtc_mode_set()
2712 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_crtc_mode_set()
2713 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_crtc_mode_set()
2715 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2717 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2720 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, in dce_v11_0_crtc_mode_set()
2721 amdgpu_crtc->pll_id, in dce_v11_0_crtc_mode_set()
2722 encoder_mode, amdgpu_encoder->encoder_id, in dce_v11_0_crtc_mode_set()
2723 adjusted_mode->clock, 0, 0, 0, 0, in dce_v11_0_crtc_mode_set()
2724 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in dce_v11_0_crtc_mode_set()
2734 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v11_0_crtc_mode_set()
2744 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_fixup()
2748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_crtc_mode_fixup()
2749 if (encoder->crtc == crtc) { in dce_v11_0_crtc_mode_fixup()
2750 amdgpu_crtc->encoder = encoder; in dce_v11_0_crtc_mode_fixup()
2751 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v11_0_crtc_mode_fixup()
2755 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v11_0_crtc_mode_fixup()
2756 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_mode_fixup()
2757 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_mode_fixup()
2765 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); in dce_v11_0_crtc_mode_fixup()
2766 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v11_0_crtc_mode_fixup()
2767 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v11_0_crtc_mode_fixup()
2768 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_crtc_mode_fixup()
2806 return -ENOMEM; in dce_v11_0_crtc_init()
2808 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); in dce_v11_0_crtc_init()
2810 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v11_0_crtc_init()
2811 amdgpu_crtc->crtc_id = index; in dce_v11_0_crtc_init()
2812 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init()
2814 amdgpu_crtc->max_cursor_width = 128; in dce_v11_0_crtc_init()
2815 amdgpu_crtc->max_cursor_height = 128; in dce_v11_0_crtc_init()
2816 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v11_0_crtc_init()
2817 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v11_0_crtc_init()
2819 switch (amdgpu_crtc->crtc_id) { in dce_v11_0_crtc_init()
2822 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2825 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2828 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2831 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2834 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2837 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2841 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_init()
2842 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_init()
2843 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_init()
2844 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_init()
2845 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); in dce_v11_0_crtc_init()
2854 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; in dce_v11_0_early_init()
2855 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; in dce_v11_0_early_init()
2859 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); in dce_v11_0_early_init()
2861 switch (adev->asic_type) { in dce_v11_0_early_init()
2863 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2864 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2867 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2868 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2872 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2873 adev->mode_info.num_dig = 6; in dce_v11_0_early_init()
2877 adev->mode_info.num_hpd = 5; in dce_v11_0_early_init()
2878 adev->mode_info.num_dig = 5; in dce_v11_0_early_init()
2882 return -EINVAL; in dce_v11_0_early_init()
2895 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2896 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v11_0_sw_init()
2902 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v11_0_sw_init()
2907 /* HPD hotplug */ in dce_v11_0_sw_init()
2908 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v11_0_sw_init()
2912 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v11_0_sw_init()
2914 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v11_0_sw_init()
2916 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2917 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2919 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v11_0_sw_init()
2920 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v11_0_sw_init()
2922 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v11_0_sw_init()
2928 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2929 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2933 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2942 return -EINVAL; in dce_v11_0_sw_init()
2953 /* Disable vblank IRQs aggressively for power-saving */ in dce_v11_0_sw_init()
2955 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v11_0_sw_init()
2957 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v11_0_sw_init()
2961 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v11_0_sw_init()
2966 adev->mode_info.mode_config_initialized = true; in dce_v11_0_sw_init()
2974 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v11_0_sw_fini()
2983 adev->mode_info.mode_config_initialized = false; in dce_v11_0_sw_fini()
3000 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_hw_init()
3001 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_hw_init()
3002 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_hw_init()
3003 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_hw_init()
3004 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, in dce_v11_0_hw_init()
3009 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v11_0_hw_init()
3012 /* initialize hpd */ in dce_v11_0_hw_init()
3015 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_init()
3016 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_init()
3031 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_fini()
3032 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_fini()
3037 flush_delayed_work(&adev->hotplug_work); in dce_v11_0_hw_fini()
3051 adev->mode_info.bl_level = in dce_v11_0_suspend()
3063 adev->mode_info.bl_level); in dce_v11_0_resume()
3068 if (adev->mode_info.bl_encoder) { in dce_v11_0_resume()
3070 adev->mode_info.bl_encoder); in dce_v11_0_resume()
3071 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v11_0_resume()
3101 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v11_0_soft_reset()
3123 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vblank_interrupt_state()
3152 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vline_interrupt_state()
3177 unsigned hpd, in dce_v11_0_set_hpd_irq_state() argument
3182 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_set_hpd_irq_state()
3183 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_set_hpd_irq_state()
3189 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3191 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3194 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3196 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3260 if (type >= adev->mode_info.num_crtc) { in dce_v11_0_set_pageflip_irq_state()
3262 return -EINVAL; in dce_v11_0_set_pageflip_irq_state()
3285 crtc_id = (entry->src_id - 8) >> 1; in dce_v11_0_pageflip_irq()
3286 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
3288 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v11_0_pageflip_irq()
3290 return -EINVAL; in dce_v11_0_pageflip_irq()
3302 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3303 works = amdgpu_crtc->pflip_works; in dce_v11_0_pageflip_irq()
3304 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v11_0_pageflip_irq()
3305 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v11_0_pageflip_irq()
3307 amdgpu_crtc->pflip_status, in dce_v11_0_pageflip_irq()
3309 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3314 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v11_0_pageflip_irq()
3315 amdgpu_crtc->pflip_works = NULL; in dce_v11_0_pageflip_irq()
3318 if(works->event) in dce_v11_0_pageflip_irq()
3319 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v11_0_pageflip_irq()
3321 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3323 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v11_0_pageflip_irq()
3324 schedule_work(&works->unpin_work); in dce_v11_0_pageflip_irq()
3330 int hpd) in dce_v11_0_hpd_int_ack() argument
3334 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_int_ack()
3335 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_hpd_int_ack()
3339 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
3349 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vblank_int_ack()
3364 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vline_int_ack()
3378 unsigned crtc = entry->src_id - 1; in dce_v11_0_crtc_irq()
3383 switch (entry->src_data[0]) { in dce_v11_0_crtc_irq()
3406 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_crtc_irq()
3418 unsigned hpd; in dce_v11_0_hpd_irq() local
3420 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_irq()
3421 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_hpd_irq()
3425 hpd = entry->src_data[0]; in dce_v11_0_hpd_irq()
3426 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3427 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
3430 dce_v11_0_hpd_int_ack(adev, hpd); in dce_v11_0_hpd_irq()
3431 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v11_0_hpd_irq()
3432 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v11_0_hpd_irq()
3474 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v11_0_encoder_mode_set()
3480 dce_v11_0_set_interleave(encoder->crtc, mode); in dce_v11_0_encoder_mode_set()
3490 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_encoder_prepare()
3494 if ((amdgpu_encoder->active_device & in dce_v11_0_encoder_prepare()
3498 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_prepare()
3500 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); in dce_v11_0_encoder_prepare()
3501 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v11_0_encoder_prepare()
3502 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v11_0_encoder_prepare()
3512 if (amdgpu_connector->router.cd_valid) in dce_v11_0_encoder_prepare()
3516 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v11_0_encoder_prepare()
3529 struct drm_device *dev = encoder->dev; in dce_v11_0_encoder_commit()
3547 dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_disable()
3548 dig->dig_encoder = -1; in dce_v11_0_encoder_disable()
3550 amdgpu_encoder->active_device = 0; in dce_v11_0_encoder_disable()
3614 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_destroy()
3616 kfree(amdgpu_encoder->enc_priv); in dce_v11_0_encoder_destroy()
3635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_encoder_add()
3637 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v11_0_encoder_add()
3638 amdgpu_encoder->devices |= supported_device; in dce_v11_0_encoder_add()
3649 encoder = &amdgpu_encoder->base; in dce_v11_0_encoder_add()
3650 switch (adev->mode_info.num_crtc) { in dce_v11_0_encoder_add()
3652 encoder->possible_crtcs = 0x1; in dce_v11_0_encoder_add()
3656 encoder->possible_crtcs = 0x3; in dce_v11_0_encoder_add()
3659 encoder->possible_crtcs = 0x7; in dce_v11_0_encoder_add()
3662 encoder->possible_crtcs = 0xf; in dce_v11_0_encoder_add()
3665 encoder->possible_crtcs = 0x1f; in dce_v11_0_encoder_add()
3668 encoder->possible_crtcs = 0x3f; in dce_v11_0_encoder_add()
3672 amdgpu_encoder->enc_priv = NULL; in dce_v11_0_encoder_add()
3674 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v11_0_encoder_add()
3675 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v11_0_encoder_add()
3676 amdgpu_encoder->devices = supported_device; in dce_v11_0_encoder_add()
3677 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v11_0_encoder_add()
3678 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v11_0_encoder_add()
3679 amdgpu_encoder->is_ext_encoder = false; in dce_v11_0_encoder_add()
3680 amdgpu_encoder->caps = caps; in dce_v11_0_encoder_add()
3682 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_encoder_add()
3694 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v11_0_encoder_add()
3695 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v11_0_encoder_add()
3698 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3699 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v11_0_encoder_add()
3702 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3706 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3720 amdgpu_encoder->is_ext_encoder = true; in dce_v11_0_encoder_add()
3721 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_add()
3724 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v11_0_encoder_add()
3751 adev->mode_info.funcs = &dce_v11_0_display_funcs; in dce_v11_0_set_display_funcs()
3771 if (adev->mode_info.num_crtc > 0) in dce_v11_0_set_irq_funcs()
3772 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3774 adev->crtc_irq.num_types = 0; in dce_v11_0_set_irq_funcs()
3775 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; in dce_v11_0_set_irq_funcs()
3777 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3778 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; in dce_v11_0_set_irq_funcs()
3780 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v11_0_set_irq_funcs()
3781 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; in dce_v11_0_set_irq_funcs()