93 	uint32_t        hpd;  member
99 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
124 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
295  * dce_v11_0_hpd_sense - hpd sense callback.
298  * @hpd: hpd (hotplug detect) pin
304 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
308 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_sense()
311 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v11_0_hpd_sense()
319  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
322  * @hpd: hpd (hotplug detect) pin
324  * Set the polarity of the hpd pin (evergreen+).
327 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
330 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
332 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_set_polarity()
335 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_set_polarity()
340 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_set_polarity()
344  * dce_v11_0_hpd_init - hpd setup callback.
348  * Setup the hpd pins used by the card (evergreen+).
349  * Enable the pin, set the polarity, and enable the hpd interrupts.
362 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_init()
367 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v11_0_hpd_init()
372 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
374 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
378 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
380 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
382 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
389 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
391 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
392 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
398  * dce_v11_0_hpd_fini - hpd tear down callback.
402  * Tear down the hpd pins used by the card (evergreen+).
403  * Disable the hpd interrupts.
416 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_fini()
419 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_fini()
421 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_fini()
423 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
2907 	/* HPD hotplug */  in dce_v11_0_sw_init()
3012 	/* initialize hpd */  in dce_v11_0_hw_init()
3177 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3182 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3183 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3189 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3191 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3194 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3196 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3330 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3334 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3335 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3339 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3341 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3418 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3425 	hpd = entry->src_data[0];  in dce_v11_0_hpd_irq()
3426 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3427 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3430 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3432 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()