Lines Matching +full:needs +full:- +full:hpd
89 uint32_t hpd; member
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
149 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
177 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
180 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
190 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
193 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
198 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
209 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_init()
210 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_init()
218 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_fini()
219 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_fini()
223 * dce_v10_0_page_flip - pageflip callback.
236 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
237 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v10_0_page_flip()
241 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
244 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
246 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
247 fb->pitches[0] / fb->format->cpp[0]); in dce_v10_0_page_flip()
249 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
252 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
255 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
261 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
262 return -EINVAL; in dce_v10_0_crtc_get_scanoutpos()
271 * dce_v10_0_hpd_sense - hpd sense callback.
274 * @hpd: hpd (hotplug detect) pin
280 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
284 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
287 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
295 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
298 * @hpd: hpd (hotplug detect) pin
300 * Set the polarity of the hpd pin (evergreen+).
303 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
306 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
308 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
311 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
316 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
320 * dce_v10_0_hpd_init - hpd setup callback.
324 * Setup the hpd pins used by the card (evergreen+).
325 * Enable the pin, set the polarity, and enable the hpd interrupts.
338 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
341 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v10_0_hpd_init()
342 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v10_0_hpd_init()
343 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v10_0_hpd_init()
348 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
350 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
354 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
356 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
358 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
365 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
367 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
368 amdgpu_irq_get(adev, &adev->hpd_irq, in dce_v10_0_hpd_init()
369 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
375 * dce_v10_0_hpd_fini - hpd tear down callback.
379 * Tear down the hpd pins used by the card (evergreen+).
380 * Disable the hpd interrupts.
393 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
396 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
398 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
400 amdgpu_irq_put(adev, &adev->hpd_irq, in dce_v10_0_hpd_fini()
401 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
417 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
426 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
467 switch (adev->asic_type) { in dce_v10_0_get_num_crtc()
504 struct drm_device *dev = encoder->dev; in dce_v10_0_program_fmt()
507 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt()
516 dither = amdgpu_connector->dither; in dce_v10_0_program_fmt()
520 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v10_0_program_fmt()
524 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v10_0_program_fmt()
525 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v10_0_program_fmt()
575 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
581 * dce_v10_0_line_buffer_adjust - Set up the line buffer
597 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust()
606 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
607 if (mode->crtc_hdisplay < 1920) { in dce_v10_0_line_buffer_adjust()
610 } else if (mode->crtc_hdisplay < 2560) { in dce_v10_0_line_buffer_adjust()
613 } else if (mode->crtc_hdisplay < 4096) { in dce_v10_0_line_buffer_adjust()
615 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
619 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
626 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
628 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
634 for (i = 0; i < adev->usec_timeout; i++) { in dce_v10_0_line_buffer_adjust()
641 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
658 * cik_get_number_of_dram_channels - get the number of dram channels
710 * dce_v10_0_dram_bandwidth - get the dram bandwidth
726 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()
728 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()
739 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
755 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()
757 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()
768 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
784 sclk.full = dfixed_const(wm->sclk); in dce_v10_0_data_return_bandwidth()
797 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
813 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v10_0_dmif_request_bandwidth()
828 * dce_v10_0_available_bandwidth - get the min available bandwidth
847 * dce_v10_0_average_bandwidth - get the average available bandwidth
868 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v10_0_average_bandwidth()
870 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v10_0_average_bandwidth()
871 src_width.full = dfixed_const(wm->src_width); in dce_v10_0_average_bandwidth()
873 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
880 * dce_v10_0_latency_watermark - get the latency watermark
895 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v10_0_latency_watermark()
896 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
897 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
903 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
908 if ((wm->vsc.full > a.full) || in dce_v10_0_latency_watermark()
909 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
910 (wm->vtaps >= 5) || in dce_v10_0_latency_watermark()
911 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v10_0_latency_watermark()
917 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
919 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v10_0_latency_watermark()
922 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v10_0_latency_watermark()
924 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v10_0_latency_watermark()
931 if (line_fill_time < wm->active_time) in dce_v10_0_latency_watermark()
934 return latency + (line_fill_time - wm->active_time); in dce_v10_0_latency_watermark()
939 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
952 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
959 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
972 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
979 * dce_v10_0_check_latency_hiding - check latency hiding
989 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
990 u32 line_time = wm->active_time + wm->blank_time; in dce_v10_0_check_latency_hiding()
996 if (wm->vsc.full > a.full) in dce_v10_0_check_latency_hiding()
999 if (lb_partitions <= (wm->vtaps + 1)) in dce_v10_0_check_latency_hiding()
1005 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v10_0_check_latency_hiding()
1014 * dce_v10_0_program_watermarks - program display watermarks
1028 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v10_0_program_watermarks()
1035 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1036 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v10_0_program_watermarks()
1037 (u32)mode->clock); in dce_v10_0_program_watermarks()
1038 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v10_0_program_watermarks()
1039 (u32)mode->clock); in dce_v10_0_program_watermarks()
1043 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1049 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1050 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1053 wm_high.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1054 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1056 wm_high.blank_time = line_time - wm_high.active_time; in dce_v10_0_program_watermarks()
1058 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1060 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1062 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1077 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1082 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1088 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1089 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1092 wm_low.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1093 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1095 wm_low.blank_time = line_time - wm_low.active_time; in dce_v10_0_program_watermarks()
1097 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1099 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1101 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1116 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1119 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
1123 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1125 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1126 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1129 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1132 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1133 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1136 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1138 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
1141 amdgpu_crtc->line_time = line_time; in dce_v10_0_program_watermarks()
1142 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v10_0_program_watermarks()
1143 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v10_0_program_watermarks()
1145 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v10_0_program_watermarks()
1149 * dce_v10_0_bandwidth_update - program display watermarks
1164 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1165 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1168 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1169 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1170 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1171 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
1181 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_connected_pins()
1182 offset = adev->mode_info.audio.pin[i].offset; in dce_v10_0_audio_get_connected_pins()
1188 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_get_connected_pins()
1190 adev->mode_info.audio.pin[i].connected = true; in dce_v10_0_audio_get_connected_pins()
1200 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_pin()
1201 if (adev->mode_info.audio.pin[i].connected) in dce_v10_0_audio_get_pin()
1202 return &adev->mode_info.audio.pin[i]; in dce_v10_0_audio_get_pin()
1210 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_afmt_audio_select_pin()
1212 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_audio_select_pin()
1215 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1218 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1219 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1220 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1226 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_latency_fields()
1229 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_latency_fields()
1236 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1241 if (connector->encoder == encoder) { in dce_v10_0_audio_write_latency_fields()
1253 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_audio_write_latency_fields()
1255 if (connector->latency_present[interlace]) { in dce_v10_0_audio_write_latency_fields()
1257 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1259 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1266 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1272 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_speaker_allocation()
1275 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_speaker_allocation()
1283 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1288 if (connector->encoder == encoder) { in dce_v10_0_audio_write_speaker_allocation()
1307 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1320 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1328 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_sad_regs()
1331 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_sad_regs()
1353 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1358 if (connector->encoder == encoder) { in dce_v10_0_audio_write_sad_regs()
1380 int max_channels = -1; in dce_v10_0_audio_write_sad_regs()
1386 if (sad->format == eld_reg_to_type[i][1]) { in dce_v10_0_audio_write_sad_regs()
1387 if (sad->channels > max_channels) { in dce_v10_0_audio_write_sad_regs()
1389 MAX_CHANNELS, sad->channels); in dce_v10_0_audio_write_sad_regs()
1391 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v10_0_audio_write_sad_regs()
1393 SUPPORTED_FREQUENCIES, sad->freq); in dce_v10_0_audio_write_sad_regs()
1394 max_channels = sad->channels; in dce_v10_0_audio_write_sad_regs()
1397 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v10_0_audio_write_sad_regs()
1398 stereo_freqs |= sad->freq; in dce_v10_0_audio_write_sad_regs()
1406 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1419 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v10_0_audio_enable()
1440 adev->mode_info.audio.enabled = true; in dce_v10_0_audio_init()
1442 adev->mode_info.audio.num_pins = 7; in dce_v10_0_audio_init()
1444 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_init()
1445 adev->mode_info.audio.pin[i].channels = -1; in dce_v10_0_audio_init()
1446 adev->mode_info.audio.pin[i].rate = -1; in dce_v10_0_audio_init()
1447 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v10_0_audio_init()
1448 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v10_0_audio_init()
1449 adev->mode_info.audio.pin[i].category_code = 0; in dce_v10_0_audio_init()
1450 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_init()
1451 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v10_0_audio_init()
1452 adev->mode_info.audio.pin[i].id = i; in dce_v10_0_audio_init()
1455 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_init()
1468 if (!adev->mode_info.audio.enabled) in dce_v10_0_audio_fini()
1471 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v10_0_audio_fini()
1472 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_fini()
1474 adev->mode_info.audio.enabled = false; in dce_v10_0_audio_fini()
1482 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_ACR()
1486 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_ACR()
1489 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1491 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1492 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1494 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1496 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1498 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1499 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1501 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1503 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1505 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1506 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1508 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1518 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_avi_infoframe()
1521 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_avi_infoframe()
1525 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1527 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1529 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1531 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1537 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_set_dto()
1540 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_set_dto()
1541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto()
1546 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1556 amdgpu_crtc->crtc_id); in dce_v10_0_audio_set_dto()
1568 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_setmode()
1571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_setmode()
1579 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1583 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1587 if (encoder->crtc) { in dce_v10_0_afmt_setmode()
1588 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode()
1589 bpc = amdgpu_crtc->bpc; in dce_v10_0_afmt_setmode()
1593 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1594 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1596 dce_v10_0_audio_set_dto(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1598 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1600 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1602 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1604 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1614 connector->name, bpc); in dce_v10_0_afmt_setmode()
1620 connector->name); in dce_v10_0_afmt_setmode()
1626 connector->name); in dce_v10_0_afmt_setmode()
1629 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1631 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1635 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1637 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1642 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1644 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1647 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1649 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1652 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1654 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1656 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1661 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1663 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1666 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1668 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1677 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1679 dce_v10_0_afmt_update_ACR(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1681 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1683 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1685 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1687 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1689 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1696 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1700 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1721 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1726 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1728 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1730 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1732 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1735 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1737 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1738 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1739 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1740 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1743 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1748 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_enable()
1751 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_enable()
1753 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1757 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1759 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1762 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1763 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1764 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1767 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1770 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
1777 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v10_0_afmt_init()
1778 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_init()
1781 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_init()
1782 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v10_0_afmt_init()
1783 if (adev->mode_info.afmt[i]) { in dce_v10_0_afmt_init()
1784 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v10_0_afmt_init()
1785 adev->mode_info.afmt[i]->id = i; in dce_v10_0_afmt_init()
1789 kfree(adev->mode_info.afmt[j]); in dce_v10_0_afmt_init()
1790 adev->mode_info.afmt[j] = NULL; in dce_v10_0_afmt_init()
1792 return -ENOMEM; in dce_v10_0_afmt_init()
1802 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_fini()
1803 kfree(adev->mode_info.afmt[i]); in dce_v10_0_afmt_fini()
1804 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_fini()
1820 struct drm_device *dev = crtc->dev; in dce_v10_0_vga_enable()
1824 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v10_0_vga_enable()
1826 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v10_0_vga_enable()
1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v10_0_vga_enable()
1834 struct drm_device *dev = crtc->dev; in dce_v10_0_grph_enable()
1838 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v10_0_grph_enable()
1840 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_grph_enable()
1848 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_do_set_base()
1862 if (!atomic && !crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
1870 target_fb = crtc->primary->fb; in dce_v10_0_crtc_do_set_base()
1875 obj = target_fb->obj[0]; in dce_v10_0_crtc_do_set_base()
1885 return -EINVAL; in dce_v10_0_crtc_do_set_base()
1895 switch (target_fb->format->format) { in dce_v10_0_crtc_do_set_base()
1952 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1963 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1979 &target_fb->format->format); in dce_v10_0_crtc_do_set_base()
1980 return -EINVAL; in dce_v10_0_crtc_do_set_base()
2016 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2019 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2021 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2023 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2025 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2027 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2029 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2030 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v10_0_crtc_do_set_base()
2037 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2042 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2047 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2048 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2049 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2050 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2051 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v10_0_crtc_do_set_base()
2052 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v10_0_crtc_do_set_base()
2054 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v10_0_crtc_do_set_base()
2055 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v10_0_crtc_do_set_base()
2059 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2060 target_fb->height); in dce_v10_0_crtc_do_set_base()
2064 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2066 viewport_w = crtc->mode.hdisplay; in dce_v10_0_crtc_do_set_base()
2067 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v10_0_crtc_do_set_base()
2068 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2072 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2074 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2075 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v10_0_crtc_do_set_base()
2092 struct drm_device *dev = crtc->dev; in dce_v10_0_set_interleave()
2097 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2098 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_set_interleave()
2102 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2108 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_load_lut()
2114 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v10_0_crtc_load_lut()
2116 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2119 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2121 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2123 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2125 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2127 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2129 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2132 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2134 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2136 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2137 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2138 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2140 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2141 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2142 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2144 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v10_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2148 r = crtc->gamma_store; in dce_v10_0_crtc_load_lut()
2149 g = r + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2150 b = g + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2152 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_load_lut()
2158 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2162 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2164 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2167 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2169 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2172 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2174 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2177 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2180 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2181 /* XXX this only needs to be programmed once per crtc at startup, in dce_v10_0_crtc_load_lut()
2184 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2186 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2192 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_pick_dig_encoder()
2194 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_pick_dig_encoder()
2196 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2201 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2206 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2213 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v10_0_pick_dig_encoder()
2219 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2224 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2235 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2237 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2243 struct drm_device *dev = crtc->dev; in dce_v10_0_pick_pll()
2248 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v10_0_pick_pll()
2249 if (adev->clock.dp_extclk) in dce_v10_0_pick_pll()
2279 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_lock_cursor()
2283 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v10_0_lock_cursor()
2288 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v10_0_lock_cursor()
2294 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_hide_cursor()
2297 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2299 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2305 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_show_cursor()
2308 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2309 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2310 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2311 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2313 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2316 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
2323 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_cursor_move_locked()
2326 amdgpu_crtc->cursor_x = x; in dce_v10_0_cursor_move_locked()
2327 amdgpu_crtc->cursor_y = y; in dce_v10_0_cursor_move_locked()
2330 x += crtc->x; in dce_v10_0_cursor_move_locked()
2331 y += crtc->y; in dce_v10_0_cursor_move_locked()
2332 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v10_0_cursor_move_locked()
2335 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v10_0_cursor_move_locked()
2339 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v10_0_cursor_move_locked()
2343 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v10_0_cursor_move_locked()
2344 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v10_0_cursor_move_locked()
2345 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_cursor_move_locked()
2346 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v10_0_cursor_move_locked()
2383 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v10_0_crtc_cursor_set2()
2384 (height > amdgpu_crtc->max_cursor_height)) { in dce_v10_0_crtc_cursor_set2()
2386 return -EINVAL; in dce_v10_0_crtc_cursor_set2()
2391 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v10_0_crtc_cursor_set2()
2392 return -ENOENT; in dce_v10_0_crtc_cursor_set2()
2409 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v10_0_crtc_cursor_set2()
2413 if (width != amdgpu_crtc->cursor_width || in dce_v10_0_crtc_cursor_set2()
2414 height != amdgpu_crtc->cursor_height || in dce_v10_0_crtc_cursor_set2()
2415 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v10_0_crtc_cursor_set2()
2416 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v10_0_crtc_cursor_set2()
2419 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v10_0_crtc_cursor_set2()
2420 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v10_0_crtc_cursor_set2()
2424 amdgpu_crtc->cursor_width = width; in dce_v10_0_crtc_cursor_set2()
2425 amdgpu_crtc->cursor_height = height; in dce_v10_0_crtc_cursor_set2()
2426 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v10_0_crtc_cursor_set2()
2427 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v10_0_crtc_cursor_set2()
2434 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_crtc_cursor_set2()
2435 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2441 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2444 amdgpu_crtc->cursor_bo = obj; in dce_v10_0_crtc_cursor_set2()
2452 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_cursor_reset()
2455 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2456 amdgpu_crtc->cursor_y); in dce_v10_0_cursor_reset()
2496 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_dpms()
2503 amdgpu_crtc->enabled = true; in dce_v10_0_crtc_dpms()
2510 amdgpu_crtc->crtc_id); in dce_v10_0_crtc_dpms()
2511 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v10_0_crtc_dpms()
2512 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v10_0_crtc_dpms()
2520 if (amdgpu_crtc->enabled) { in dce_v10_0_crtc_dpms()
2526 amdgpu_crtc->enabled = false; in dce_v10_0_crtc_dpms()
2550 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_disable()
2556 if (crtc->primary->fb) { in dce_v10_0_crtc_disable()
2560 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v10_0_crtc_disable()
2574 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_crtc_disable()
2575 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2576 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2577 i != amdgpu_crtc->crtc_id && in dce_v10_0_crtc_disable()
2578 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2586 switch (amdgpu_crtc->pll_id) { in dce_v10_0_crtc_disable()
2591 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2598 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_disable()
2599 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_disable()
2600 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_disable()
2601 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_disable()
2611 if (!amdgpu_crtc->adjusted_clock) in dce_v10_0_crtc_mode_set()
2612 return -EINVAL; in dce_v10_0_crtc_mode_set()
2621 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v10_0_crtc_mode_set()
2631 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_mode_fixup()
2635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_crtc_mode_fixup()
2636 if (encoder->crtc == crtc) { in dce_v10_0_crtc_mode_fixup()
2637 amdgpu_crtc->encoder = encoder; in dce_v10_0_crtc_mode_fixup()
2638 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v10_0_crtc_mode_fixup()
2642 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v10_0_crtc_mode_fixup()
2643 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_mode_fixup()
2644 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_mode_fixup()
2652 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2653 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
2654 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v10_0_crtc_mode_fixup()
2655 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v10_0_crtc_mode_fixup()
2693 return -ENOMEM; in dce_v10_0_crtc_init()
2695 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); in dce_v10_0_crtc_init()
2697 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v10_0_crtc_init()
2698 amdgpu_crtc->crtc_id = index; in dce_v10_0_crtc_init()
2699 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
2701 amdgpu_crtc->max_cursor_width = 128; in dce_v10_0_crtc_init()
2702 amdgpu_crtc->max_cursor_height = 128; in dce_v10_0_crtc_init()
2703 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v10_0_crtc_init()
2704 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v10_0_crtc_init()
2706 switch (amdgpu_crtc->crtc_id) { in dce_v10_0_crtc_init()
2709 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2712 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2715 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2718 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2721 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2724 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2728 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_init()
2729 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_init()
2730 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_init()
2731 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_init()
2732 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); in dce_v10_0_crtc_init()
2741 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; in dce_v10_0_early_init()
2742 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; in dce_v10_0_early_init()
2746 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); in dce_v10_0_early_init()
2748 switch (adev->asic_type) { in dce_v10_0_early_init()
2751 adev->mode_info.num_hpd = 6; in dce_v10_0_early_init()
2752 adev->mode_info.num_dig = 7; in dce_v10_0_early_init()
2756 return -EINVAL; in dce_v10_0_early_init()
2769 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2770 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v10_0_sw_init()
2776 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v10_0_sw_init()
2781 /* HPD hotplug */ in dce_v10_0_sw_init()
2782 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v10_0_sw_init()
2786 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v10_0_sw_init()
2788 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v10_0_sw_init()
2790 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2791 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2793 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v10_0_sw_init()
2794 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v10_0_sw_init()
2796 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v10_0_sw_init()
2802 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2803 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2806 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2815 return -EINVAL; in dce_v10_0_sw_init()
2826 /* Disable vblank IRQs aggressively for power-saving */ in dce_v10_0_sw_init()
2828 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v10_0_sw_init()
2830 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v10_0_sw_init()
2834 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v10_0_sw_init()
2839 adev->mode_info.mode_config_initialized = true; in dce_v10_0_sw_init()
2847 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v10_0_sw_fini()
2856 adev->mode_info.mode_config_initialized = false; in dce_v10_0_sw_fini()
2872 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v10_0_hw_init()
2874 /* initialize hpd */ in dce_v10_0_hw_init()
2877 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_init()
2878 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_init()
2893 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_fini()
2894 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_fini()
2899 flush_delayed_work(&adev->hotplug_work); in dce_v10_0_hw_fini()
2913 adev->mode_info.bl_level = in dce_v10_0_suspend()
2925 adev->mode_info.bl_level); in dce_v10_0_resume()
2930 if (adev->mode_info.bl_encoder) { in dce_v10_0_resume()
2932 adev->mode_info.bl_encoder); in dce_v10_0_resume()
2933 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v10_0_resume()
2970 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
2992 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
3021 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3046 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3051 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3052 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3058 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3060 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3063 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3065 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3129 if (type >= adev->mode_info.num_crtc) { in dce_v10_0_set_pageflip_irq_state()
3131 return -EINVAL; in dce_v10_0_set_pageflip_irq_state()
3154 crtc_id = (entry->src_id - 8) >> 1; in dce_v10_0_pageflip_irq()
3155 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
3157 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v10_0_pageflip_irq()
3159 return -EINVAL; in dce_v10_0_pageflip_irq()
3171 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3172 works = amdgpu_crtc->pflip_works; in dce_v10_0_pageflip_irq()
3173 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dce_v10_0_pageflip_irq()
3174 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v10_0_pageflip_irq()
3176 amdgpu_crtc->pflip_status, in dce_v10_0_pageflip_irq()
3178 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3183 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v10_0_pageflip_irq()
3184 amdgpu_crtc->pflip_works = NULL; in dce_v10_0_pageflip_irq()
3187 if (works->event) in dce_v10_0_pageflip_irq()
3188 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v10_0_pageflip_irq()
3190 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3192 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v10_0_pageflip_irq()
3193 schedule_work(&works->unpin_work); in dce_v10_0_pageflip_irq()
3199 int hpd) in dce_v10_0_hpd_int_ack() argument
3203 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3204 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3208 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3210 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3218 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3233 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3247 unsigned crtc = entry->src_id - 1; in dce_v10_0_crtc_irq()
3251 switch (entry->src_data[0]) { in dce_v10_0_crtc_irq()
3274 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_crtc_irq()
3286 unsigned hpd; in dce_v10_0_hpd_irq() local
3288 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_irq()
3289 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_hpd_irq()
3293 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3294 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3295 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3298 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3299 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v10_0_hpd_irq()
3300 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()
3343 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v10_0_encoder_mode_set()
3349 dce_v10_0_set_interleave(encoder->crtc, mode); in dce_v10_0_encoder_mode_set()
3359 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_encoder_prepare()
3363 if ((amdgpu_encoder->active_device & in dce_v10_0_encoder_prepare()
3367 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_prepare()
3369 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); in dce_v10_0_encoder_prepare()
3370 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v10_0_encoder_prepare()
3371 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3381 if (amdgpu_connector->router.cd_valid) in dce_v10_0_encoder_prepare()
3385 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v10_0_encoder_prepare()
3398 struct drm_device *dev = encoder->dev; in dce_v10_0_encoder_commit()
3416 dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_disable()
3417 dig->dig_encoder = -1; in dce_v10_0_encoder_disable()
3419 amdgpu_encoder->active_device = 0; in dce_v10_0_encoder_disable()
3483 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_destroy()
3485 kfree(amdgpu_encoder->enc_priv); in dce_v10_0_encoder_destroy()
3504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_encoder_add()
3506 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v10_0_encoder_add()
3507 amdgpu_encoder->devices |= supported_device; in dce_v10_0_encoder_add()
3518 encoder = &amdgpu_encoder->base; in dce_v10_0_encoder_add()
3519 switch (adev->mode_info.num_crtc) { in dce_v10_0_encoder_add()
3521 encoder->possible_crtcs = 0x1; in dce_v10_0_encoder_add()
3525 encoder->possible_crtcs = 0x3; in dce_v10_0_encoder_add()
3528 encoder->possible_crtcs = 0xf; in dce_v10_0_encoder_add()
3531 encoder->possible_crtcs = 0x3f; in dce_v10_0_encoder_add()
3535 amdgpu_encoder->enc_priv = NULL; in dce_v10_0_encoder_add()
3537 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v10_0_encoder_add()
3538 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v10_0_encoder_add()
3539 amdgpu_encoder->devices = supported_device; in dce_v10_0_encoder_add()
3540 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v10_0_encoder_add()
3541 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v10_0_encoder_add()
3542 amdgpu_encoder->is_ext_encoder = false; in dce_v10_0_encoder_add()
3543 amdgpu_encoder->caps = caps; in dce_v10_0_encoder_add()
3545 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_encoder_add()
3557 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v10_0_encoder_add()
3558 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v10_0_encoder_add()
3561 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3562 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v10_0_encoder_add()
3565 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3569 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3583 amdgpu_encoder->is_ext_encoder = true; in dce_v10_0_encoder_add()
3584 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_add()
3587 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v10_0_encoder_add()
3614 adev->mode_info.funcs = &dce_v10_0_display_funcs; in dce_v10_0_set_display_funcs()
3634 if (adev->mode_info.num_crtc > 0) in dce_v10_0_set_irq_funcs()
3635 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3637 adev->crtc_irq.num_types = 0; in dce_v10_0_set_irq_funcs()
3638 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; in dce_v10_0_set_irq_funcs()
3640 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3641 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; in dce_v10_0_set_irq_funcs()
3643 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v10_0_set_irq_funcs()
3644 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; in dce_v10_0_set_irq_funcs()