89 	uint32_t        hpd;  member
95 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
271  * dce_v10_0_hpd_sense - hpd sense callback.
274  * @hpd: hpd (hotplug detect) pin
280 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
284 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_sense()
287 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v10_0_hpd_sense()
295  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
298  * @hpd: hpd (hotplug detect) pin
300  * Set the polarity of the hpd pin (evergreen+).
303 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
306 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
308 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_set_polarity()
311 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_set_polarity()
316 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_set_polarity()
320  * dce_v10_0_hpd_init - hpd setup callback.
324  * Setup the hpd pins used by the card (evergreen+).
325  * Enable the pin, set the polarity, and enable the hpd interrupts.
338 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_init()
343 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v10_0_hpd_init()
348 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
350 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
354 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
356 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
358 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
365 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
367 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
369 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
375  * dce_v10_0_hpd_fini - hpd tear down callback.
379  * Tear down the hpd pins used by the card (evergreen+).
380  * Disable the hpd interrupts.
393 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_fini()
396 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_fini()
398 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_fini()
401 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
2781 	/* HPD hotplug */  in dce_v10_0_sw_init()
2874 	/* initialize hpd */  in dce_v10_0_hw_init()
3046 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
3051 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
3052 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3058 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3060 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3063 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3065 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3199 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3203 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3204 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3208 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3210 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3286 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3293 	hpd = entry->src_data[0];  in dce_v10_0_hpd_irq()
3294 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3295 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3298 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3300 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()