Lines Matching defs:amdgpu_crtc
459 struct amdgpu_crtc { struct
460 struct drm_crtc base;
461 int crtc_id;
462 bool enabled;
463 bool can_tile;
464 uint32_t crtc_offset;
465 struct drm_gem_object *cursor_bo;
466 uint64_t cursor_addr;
467 int cursor_x;
468 int cursor_y;
469 int cursor_hot_x;
470 int cursor_hot_y;
471 int cursor_width;
472 int cursor_height;
473 int max_cursor_width;
474 int max_cursor_height;
475 enum amdgpu_rmx_type rmx_type;
476 u8 h_border;
477 u8 v_border;
478 fixed20_12 vsc;
479 fixed20_12 hsc;
480 struct drm_display_mode native_mode;
481 u32 pll_id;
483 struct amdgpu_flip_work *pflip_works;
484 enum amdgpu_flip_status pflip_status;
485 int deferred_flip_completion;
487 struct dm_irq_params dm_irq_params;
489 struct amdgpu_atom_ss ss;
490 bool ss_enabled;
491 u32 adjusted_clock;
492 int bpc;
493 u32 pll_reference_div;
494 u32 pll_post_div;
495 u32 pll_flags;
496 struct drm_encoder *encoder;
497 struct drm_connector *connector;
499 u32 line_time;
500 u32 wm_low;
501 u32 wm_high;
502 u32 lb_vblank_lead_lines;
503 struct drm_display_mode hw_mode;
505 struct hrtimer vblank_timer;
506 enum amdgpu_interrupt_state vsync_timer_enabled;
508 int otg_inst;
509 struct drm_pending_vblank_event *event;
511 bool wb_pending;
512 bool wb_enabled;
513 struct drm_writeback_connector *wb_conn;