Lines Matching defs:amdgpu_gfx_config

182 struct amdgpu_gfx_config {  struct
183 	unsigned max_shader_engines;
184 	unsigned max_tile_pipes;
185 	unsigned max_cu_per_sh;
186 	unsigned max_sh_per_se;
187 	unsigned max_backends_per_se;
188 	unsigned max_texture_channel_caches;
189 	unsigned max_gprs;
190 	unsigned max_gs_threads;
191 	unsigned max_hw_contexts;
192 	unsigned sc_prim_fifo_size_frontend;
193 	unsigned sc_prim_fifo_size_backend;
194 	unsigned sc_hiz_tile_fifo_size;
195 	unsigned sc_earlyz_tile_fifo_size;
197 	unsigned num_tile_pipes;
198 	unsigned backend_enable_mask;
199 	unsigned mem_max_burst_length_bytes;
200 	unsigned mem_row_size_in_kb;
201 	unsigned shader_engine_tile_size;
202 	unsigned num_gpus;
203 	unsigned multi_gpu_tile_size;
204 	unsigned mc_arb_ramcfg;
205 	unsigned num_banks;
206 	unsigned num_ranks;
207 	unsigned gb_addr_config;
208 	unsigned num_rbs;
209 	unsigned gs_vgt_table_depth;
210 	unsigned gs_prim_buffer_depth;
212 	uint32_t tile_mode_array[32];
213 	uint32_t macrotile_mode_array[16];
215 	struct gb_addr_config gb_addr_config_fields;
216 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
219 	uint32_t double_offchip_lds_buf;
221 	uint32_t db_debug2;
223 	uint32_t num_sc_per_sh;
224 	uint32_t num_packer_per_sc;
225 	uint32_t pa_sc_tile_steering_override;
227 	bool ta_cntl2_truncate_coord_mode;
228 	uint64_t tcc_disabled_mask;
229 	uint32_t gc_num_tcp_per_sa;
230 	uint32_t gc_num_sdp_interface;
231 	uint32_t gc_num_tcps;
232 	uint32_t gc_num_tcp_per_wpg;
233 	uint32_t gc_tcp_l1_size;
234 	uint32_t gc_num_sqc_per_wgp;
235 	uint32_t gc_l1_instruction_cache_size_per_sqc;
236 	uint32_t gc_l1_data_cache_size_per_sqc;
237 	uint32_t gc_gl1c_per_sa;
238 	uint32_t gc_gl1c_size_per_instance;
239 	uint32_t gc_gl2c_per_gpu;
240 	uint32_t gc_tcp_size_per_cu;
241 	uint32_t gc_num_cu_per_sqc;
242 	uint32_t gc_tcc_size;