342 struct amdgpu_gfx {  struct
344 	struct amdgpu_gfx_config	config;  argument
345 	struct amdgpu_rlc		rlc;
346 	struct amdgpu_pfp		pfp;
347 	struct amdgpu_ce		ce;
348 	struct amdgpu_me		me;
349 	struct amdgpu_mec		mec;
350 	struct amdgpu_mec_bitmap	mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
351 	struct amdgpu_kiq		kiq[AMDGPU_MAX_GC_INSTANCES];
352 	struct amdgpu_imu		imu;
353 	bool				rs64_enable; /* firmware format */
354 	const struct firmware		*me_fw;	/* ME firmware */
355 	uint32_t			me_fw_version;
356 	const struct firmware		*pfp_fw; /* PFP firmware */
357 	uint32_t			pfp_fw_version;
358 	const struct firmware		*ce_fw;	/* CE firmware */
359 	uint32_t			ce_fw_version;
360 	const struct firmware		*rlc_fw; /* RLC firmware */
361 	uint32_t			rlc_fw_version;
362 	const struct firmware		*mec_fw; /* MEC firmware */
363 	uint32_t			mec_fw_version;
364 	const struct firmware		*mec2_fw; /* MEC2 firmware */
365 	uint32_t			mec2_fw_version;
366 	const struct firmware		*imu_fw; /* IMU firmware */
367 	uint32_t			imu_fw_version;
368 	uint32_t			me_feature_version;
369 	uint32_t			ce_feature_version;
370 	uint32_t			pfp_feature_version;
371 	uint32_t			rlc_feature_version;
372 	uint32_t			rlc_srlc_fw_version;
373 	uint32_t			rlc_srlc_feature_version;
374 	uint32_t			rlc_srlg_fw_version;
375 	uint32_t			rlc_srlg_feature_version;
376 	uint32_t			rlc_srls_fw_version;
377 	uint32_t			rlc_srls_feature_version;
378 	uint32_t			rlcp_ucode_version;
379 	uint32_t			rlcp_ucode_feature_version;
380 	uint32_t			rlcv_ucode_version;
404 	const struct amdgpu_gfx_funcs	*funcs;  argument
424 	struct amdgpu_gfx_ras		*ras;  argument
439 struct amdgpu_gfx_ras_reg_entry {  argument