8  * and/or sell copies of the Software, and to permit persons to whom the
12  * all copies or substantial portions of the Software.
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 /* AT24CM02 and M24M02-R have a 256-byte write page size.
31 #define EEPROM_PAGE_MASK   (EEPROM_PAGE_SIZE - 1)
35 /* EEPROM memory addresses are 19-bits long, which can
37  * The upper 3 bits are sent as part of the 7-bit
38  * "Device Type Identifier"--an I2C concept, which for EEPROM devices
39  * is hard-coded as 1010b, indicating that it is an EEPROM
40  * device--this is the wire format, followed by the upper
41  * 3 bits of the 19-bit address, followed by the direction,
42  * followed by two bytes holding the rest of the 16-bits of
47  * These bits are compared to how pins 1-3 of the part are connected,
52  * which is exactly the EEPROM memory address, or offset,
55  * For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes,
56  * using an 18-bit address, bit 17 to 0 and thus would use all but one bit of
58  * pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to
59  * either Vcc or GND. This would allow for up to two 2-Mbit parts on
63  * For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or
67  * 2-Mbit EEPROM devices on the same bus, but see one contiguous
72  * This addressing you encode in the 32-bit "eeprom_addr" below,
73  * namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For
85  * (M24M02-DR device only, which we do not use), change the "7" to
99 			.len = EEPROM_OFFSET_SIZE,  in __amdgpu_eeprom_xfer()
108 	u16 len;  in __amdgpu_eeprom_xfer()  local
111 	      buf_size -= len, eeprom_addr += len, eeprom_buf += len) {  in __amdgpu_eeprom_xfer()
132 			 * condition, so that the self-timed write  in __amdgpu_eeprom_xfer()
136 			len = min(EEPROM_PAGE_SIZE - (eeprom_addr &  in __amdgpu_eeprom_xfer()
142 			 * device--they are simply sequenced out.  in __amdgpu_eeprom_xfer()
144 			len = buf_size;  in __amdgpu_eeprom_xfer()
146 		msgs[1].len = len;  in __amdgpu_eeprom_xfer()
149 		/* This constitutes a START-STOP transaction.  in __amdgpu_eeprom_xfer()
157 			 * self-writing cycle, tWR (tW), is 10 ms.  in __amdgpu_eeprom_xfer()
168 	return r < 0 ? r : eeprom_buf - p;  in __amdgpu_eeprom_xfer()
172  * amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device
179  * Returns the number of bytes read/written; -errno on error.
184 	const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;  in amdgpu_eeprom_xfer()
185 	u16 limit;  in amdgpu_eeprom_xfer()  local
190 		limit = 0;  in amdgpu_eeprom_xfer()
192 		limit = quirks->max_read_len;  in amdgpu_eeprom_xfer()
194 		limit = quirks->max_write_len;  in amdgpu_eeprom_xfer()
196 	if (limit == 0) {  in amdgpu_eeprom_xfer()
199 	} else if (limit <= EEPROM_OFFSET_SIZE) {  in amdgpu_eeprom_xfer()
200 		dev_err_ratelimited(&i2c_adap->dev,  in amdgpu_eeprom_xfer()
204 		return -EINVAL;  in amdgpu_eeprom_xfer()
207 	/* The "limit" includes all data bytes sent/received,  in amdgpu_eeprom_xfer()
211 	limit -= EEPROM_OFFSET_SIZE;  in amdgpu_eeprom_xfer()
213 	      buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {  in amdgpu_eeprom_xfer()
214 		ps = min(limit, buf_size);  in amdgpu_eeprom_xfer()